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asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 1 - general description the AK4588 is a single chip codec that includes two channels of adc and eight channels of dac. the adc outputs 24bit data and the dac accepts up to 24bit input data. the adc has the enhanced dual bit architecture with wide dynamic range. the dac introduces the new developed advanced multi-bit architecture, and achieves wider dynamic range and lower outband noise. the AK4588 has a dynamic range of 102db for adc, 106db for dac and is well suited for digital surround for home theater and car audio. the AK4588 also has the balance volume control corresponding to the dolby digital (ac-3) system. the also has digital audio receiver (dir) and transmitter (dit) compatible with 192khz, 24bits. the dir has 8-channel input selector and can automatically detect a non-pcm bit stream. the AK4588 provides a fully compatibility of hardware and software with the ak4628 and the ak4114. *ac-3 is a trademark of dolby laboratories. features adc/dac part 2ch 24bit adc - 64x oversampling - sampling rate up to 96khz - linear phase digital anti-alias filter - single-ended input - s/(n+d): 92db - dynamic range, s/n: 102db - digital hpf for offset cancellation - overflow flag 8ch 24bit dac - 128x oversampling - sampling rate up to 192khz - 24bit 8 times digital filter - single-ended outputs - on-chip switched-capacitor filter - s/(n+d): 90db - dynamic range, s/n: 106db - individual channel digital volume with 128 levels and 0.5db step - soft mute - zero detect function high jitter tolerance extenal master clock input: - 256fs, 384fs, 512fs (fs=32khz 48khz) - 128fs, 192fs, 256fs (fs=64khz 96khz) - 128fs (fs=120khz 192khz) 2/8-channel audio codec with di r AK4588 = preliminary =
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 2 - dir/dit part aes3, iec60958, s/pdif, eiaj cp1201 compatible low jitter analog pll pll lock range : 32khz to 192khz clock source: pll or x'tal 8-channel receiver input 2-channel transmission output (through output or dit) auxiliary digital input de-emphasis for 32khz, 44.1khz, 48khz and 96khz detection functions - non-pcm bit stream detection - dts-cd bit stream detection - sampling frequency detection (32khz, 44.1khz, 48khz, 88.2khz, 96khz, 176.4khz, 192khz) - unlock & parity error detection - validity flag detection up to 24bit audio data format audio i/f: master or slave mode 40-bit channel status buffer burst preamble bit pc and pd buffer for non-pcm bit stream q-subcode buffer for cd bit stream serial p i/f two master clock outputs: 64fs/128fs/256fs/512fs ttl level digital i/f 4-wire serial and i 2 c bus p i/f for mode setting operating voltage: 4.5 to 5.5v with 5v tolerance 80pin lqfp package
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 3 - block diagram in p ut selector clock recovery clock generator daif decoder a c-3/mpeg detect dem p i/f a udio i/f x'tal oscillator pdn int0 lrck2 bick2 sdto2 daux2 mcko2 xto xti r pvdd pvss cdti cdto cclk csn dvdd dvss tvdd mcko1 i2c rx0 rx1 rx2 rx3 rx4 rx5 rx6 rx7 dit tx0 error & detect status int1 q-subcode buffe r tx1 b,c,u, vout 8 to 3 vin audio i/f lpf lpf lpf lpf lpf lpf lout1 rout1 lout2 rout2 lout3 rout3 dac datt dem adc hpf adc hpf rin lin lrck1 bick1 sdti1 sdti2 sdti3 daux1 mclk lrck bick sdout sdin1 sdin2 sdin3 mclk sdto1 format converter sdti4 sdin4 lpf lpf lout4 rout4 dac datt dem dac datt dem dac datt dem dac datt dem dac datt dem dac datt dem dac datt dem a vdd a vss
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 4 - ordering guide AK4588vq -10 +70 c 80pin lqfp(0.5mm pitch) akd4588 evaluation board for AK4588 pin layout (top view) cclk/scl cdti/sda csn daux1 sdti4 sdti3 sdti2 sdti1 xtl1 xtl0 pdn master dzf2 dzf1 lout4 nc rout4 nc lout3 nc 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 int1 bout tvdd dvdd dvss xto xti test3 mcko2 mcko1 cout uout vout sdto2 bick2 lrck2 sdto1 bick1 lrck1 cdto test1 rx1 nc rx0 avss avdd vrefh vcom rin lin nc rout1 nc lout1 nc rout2 nc lout2 nc rout3 int0 tx1 tx0 mclk vin daux2 i2c rx7 cad1 rx6 cad0 rx5 test2 rx4 pvdd r pvss rx3 nc rx2
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 5 - compatibility with ak4628 + ak4114 functions ak4628+ ak4114 AK4588 parallel control mode yes no tdm0, dfs0, dzfe, sdos, smute pins available not available 4 wire serial (i2c=?l?) ak4628: set by cad1/0 pins ak4114: fixed to ?00? adc/dac part: set by cad1/0 pins dir/dit part: fixed to ?00? chip address(*) i 2 c bus (i2c=?h?) ak4628: set by cad1/0 pins ak4114: set by cad1/0 pins adc/dac part: set by cad1/0 pins dir/dit part: fixed to ?00? (*) the AK4588 has two register maps including adc/dac part (compatible with the AK4588) and dir/dit part (compatible with ak4114). each register is selected by chip address.
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 6 - pin/function no. pin name i/o function 1 int1 o interrupt 1 pin 2 bout o block-start output pin for receiver input ?h? during first 40 flames. 3 tvdd - output buffer power supply pin, 2.7v 5.5v 4 dvdd - digital power supply pin, 3.3v 5 dvss - digital ground pin 6 xto o x'tal output pin 7 xti i x'tal input pin 8 test3 i test 3 pin this pin should be connected to dvss. 9 mcko2 o master clock output 2 pin 10 mcko1 o master clock output 1 pin 11 cout o c-bit output pin for receiver input 12 uout o u-bit output pin for receiver input 13 vout o v-bit output pin for receiver input 14 sdto2 o audio serial data output pin (dir/dit part) 15 bick2 i/o audio serial data clock pin (dir/dit part) 16 lrck2 i/o channel clock pin (dir/dit part) 17 sdto1 o audio serial data output pin (adc/dac part) 18 bick1 i/o audio serial data clock pin (adc/dac part) 19 lrck1 i/o input channel clock pin 20 cdto o control data output pin in serial mode, i2c= ?l?. cclk i control data clock pin in serial mode, i2c= ?l? 21 scl i control data clock pin in serial mode, i2c= ?h? cdti i control data input pin in serial mode, i2c= ?l?. 22 sda i/o control data pin in serial mode, i2c= ?h?. i chip select pin in serial mode, i2c=?l?. 23 csn i this pin should be connected to dvss, i2c=?h?. 24 daux1 i aux audio serial data input pin (adc/dac part) 25 sdti4 i dac4 audio serial data input pin 26 sdti3 i dac3 audio serial data input pin 27 sdti2 i dac2 audio serial data input pin 28 sdti1 i dac1 audio serial data input pin 29 xtl1 i x?tal frequency select 0 pin 30 xtl0 i x?tal frequency select 1 pin
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 7 - no. pin name i/o function 31 pdn i power-down mode pin when ?l?, the AK4588 is powered-down, all output pin goes ?l?, all registers are reset. when cad1/0 pins are changed, the AK4588 should be reset by pdn pin. 32 master i master mode select pin ?h?: master mode, ?l?: slave mode dzf2 o zero input detect 2 pin (note 1) when the input data of the group 1 follow total 8192 lrck cycles with ?0? input data, this pin goes to ?h?. and when rstn bit is ?0?, pwdan bit is ?0?, this pin goes to ?h?. it always is in ?l? when p/s is ?h?. 33 ovf o analog input overflow detect pin (note 2) this pin goes to ?h? if the analog input of lch or rch overflows. 34 dzf1 o zero input detect 1 pin (note 1) when the input data of the group 1 follow total 8192 lrck cycles with ?0? input data, this pin goes to ?h?. and when rstn bit is ?0?, pwdan bit is ?0?, this pin goes to ?h?. output is selected by setting dzfe pin when p/s is ?h?. 35 lout4 o dac4 lch analog output pin 36 nc - no connect no internal bonding. 37 rout4 o dac4 rch analog output pin 38 nc - no connect no internal bonding. 39 lout3 o dac3 lch analog output pin 40 nc - no connect no internal bonding. 41 rout3 o dac3 rch analog output pin 42 nc - no connect no internal bonding. 43 lout2 o dac2 lch analog output pin 44 nc - no connect no internal bonding. 45 rout2 o dac2 rch analog output pin 46 nc - no connect no internal bonding. 47 lout1 o dac1 lch analog output pin 48 nc - no connect no internal bonding. 49 rout1 o dac1 rch analog output pin 50 nc - no connect no internal bonding. 51 lin i lch analog input pin 52 rin i rch analog input pin 53 vcom - common voltage output pin 2.2 f capacitor should be connected to pvss externally. 54 vrefh - positive voltage reference input pin, avdd notes: 1. the group 1 and 2 can be selected by dzfm2-0 bits. 2. this pin becomes ovfe bit if ovfe bit is set to 1.
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 8 - no. pin name i/o function 55 avdd - analog power supply pin, 4.5v 5.5v 56 avss - analog ground pin, 0v 57 rx0 i receiver channel 0 pin (internal biased pin) this channel is default in serial mode. 58 nc - no connect this pin should be connected to pvss. 59 rx1 i receiver channel 1 pin (internal biased pin) 60 test1 i test 1 pin this pin should be connected to pvss. 61 rx2 i receiver channel 2 pin (internal biased pin) 62 nc - no connect this pin should be connected to pvss. 63 rx3 i receiver channel 3 pin (internal biased pin) 64 pvss - pll ground pin 65 r - external resistor pin 12k ? +/-1% resistor should be connected to pvss externally. 66 pvdd - pll power supply pin, 5.0v 67 rx4 i receiver channel 4 pin (internal biased pin) 68 test2 i test 2 pin this pin should be connected to pvss. 69 rx5 i receiver channel 5 pin (internal biased pin) 70 cad0 i chip address 0 pin (adc/dac part) 71 rx6 i receiver channel 6 pin (internal biased pin) 72 cad1 i chip address 1 pin (adc/dac part) 73 rx7 i receiver channel 7 pin (internal biased pin) 74 i2c i control mode select pin. ?l?: 4-wire serial, ?h?: i 2 c bus 75 daux2 i auxiliary audio data input pin (dir/dit part) 76 vin i v-bit input pin for transmitter output 77 mclk i master clock input pin 78 tx0 o transmit channel (through data) output 0 pin 79 tx1 o transmit channel output1 pin when tx bit = ?0?, transmit channel (through data) output 1 pin. when tx bit = ?1?, transmit channel (daux2 data) output pin (default). 80 int0 o interrupt 0 pin notes: 3. all input pins except internal biased pins and internal pull-down pin should not be left floating.
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 9 - bsolute maximum rat ings (avss, dvss, pvss=0v; note 4) parameter symbol min max units power supplies analog digital pll output buffer |avss-dvss| (note 5) |avss-pvss| (note 5) avdd dvdd pvdd tvdd ? gnd1 ? gnd2 -0.3 -0.3 -0.3 -0.3 - - 6.0 6.0 6.0 6.0 0.3 0.3 v v v v v v input current (any pins except for supplies) iin - 10 ma analog input voltage (lin, rin pins) vina -0.3 avdd+0.3 v digital input voltage except lrck1-2, bick1-2, rx0-7, cad0-1, test1-2 pins vind1 -0.3 dvdd+0.3 v lrck1-2, bick1-2 pins vind2 -0.3 tvdd+0.3 v rx0-7, cad0-1, test1-2 vind3 -0.3 pvdd+0.3 v ambient temperature (power applied) ta -10 70 c storage temperature tstg -65 150 c notes: 4. all voltages with respect to ground. 5.avss, dvss and pvss must be connected to the same analog ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (avss, dvss, pvss=0v; note 6) parameter symbol min typ max units power supplies (note 6) analog digital pll output buffer avdd dvdd pvdd tvdd 4.5 4.5 4.5 2.7 5.0 5.0 5.0 5.0 5.5 avdd avdd dvdd v v v v notes: 6. all voltages with respect to ground. 7. the power up sequence between avdd, dvdd, pvdd and tvdd is not critical. to save leak current in power down mode, avdd, dvdd, pvdd become the same voltage as much as possible. warning: akm assumes no responsibility for the usage beyond the conditions in this datasheet.
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 10 - analog characteristics (ta=25 c; avdd, dvdd, pvdd, tvdd=5v; avss, dvss=0v; vrefh=avdd; fs=48khz; bick=64fs; signal frequency=1khz; 24bit data; measurement frequency=20hz 20khz at fs=48khz, 20hz~40khz at fs=96khz; 20hz~40khz at fs=192khz, unless otherwise specified) parameter min typ max units adc analog input characteristics resolution 24 bits s/(n+d) (-0.5dbfs) fs=48khz fs=96khz 84 - 92 86 db db dr (-60dbfs) fs=48khz, a-weighted fs=96khz fs=96khz, a-weighted 94 88 93 102 96 102 db db db s/n (note 8) fs=48khz, a-weighted fs=96khz fs=96khz, a-weighted 94 88 93 102 96 102 db db db interchannel isolation 90 110 db dc accuracy interchannel gain mismatch 0.2 0.3 db gain drift 20 - ppm/ c input voltage ain=0.62xvrefh 2.90 3.10 3.30 vpp input resistance fs=48khz fs=96khz 15 tbd 25 16 k ? k ? power supply rejection (note 9) 50 db dac analog output characteristics resolution 24 bits s/(n+d) fs=48khz fs=96khz fs=192khz 80 78 - 90 88 tbd db db db dr (-60dbfs) fs=48khz, a-weighted fs=96khz, a-weighted fs=192khz, a-weighted 95 94 - 106 106 tbd db db db s/n (note 10) fs=48khz, a-weighted fs=96khz, a-weighted fs=192khz, a-weighted 95 94 - 106 106 tbd db db db interchannel isolation 90 110 db dc accuracy interchannel gain mismatch 0.2 0.5 db gain drift 20 - ppm/ c output voltage aout=0.6xvrefh 2.75 3.0 3.25 vpp load resistance 5 k ? power supply rejection (note 9) 50 db power supplies power supply current normal operation (pdn = ?h?) (note 11) avdd fs=48khz fs=96khz pvdd dvdd+tvdd fs=48khz (note 12) fs=96khz fs=192khz power-down mode (pdn = ?l?) (note 13) tbd tbd tbd tbd tbd tbd 80 ma ma ma ma ma ma a
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 11 - notes: 8. s/n measured by ccir-arm is 96db(@fs=48khz). 9. psr is applied to avdd, dvdd, pvdd and tvdd with 1khz, 50mvpp. vrefh pin is held a constant voltage. 10. s/n measured by ccir-arm is 102db(@fs=48khz). 11. c l =20pf, x'tal=24.576mhz, cm1-0= ?10?, ocks= ?10?. 12. tvdd=3ma(typ). 13. in the power-down mode. rx inputs are open and all digital input pins including clock pins (mclk, bick, lrck) are held dvss. filter characteristics (ta=25 c; avdd, dvdd=4.5 5.5v; tvdd=2.7 5.5v; fs=48khz) parameter symbol min typ max units adc digital filter (decimation lpf): passband (note 15) 0.1db -0.2db -3.0db pb 0 - - 20.0 23.0 18.9 - - khz khz khz stopband sb 29.4 khz passband ripple pr 0.04 db stopband attenuation sa 65 db group delay (note 15) gd 19.1 1/fs group delay distortion ? gd 0 s adc digital filter (hpf): frequency response (note 14) -3db -0.1db fr 1.0 6.5 hz hz dac digital filter: passband (note 15) -0.1db -6.0db pb 0 - 24.0 21.8 - khz khz stopband sb 26.2 khz passband ripple pr 0.02 db stopband attenuation sa 54 db group delay (note 15) gd 19.2 1/fs dac digital filter + analog filter: frequency response: 0 20.0khz 40.0khz (note 16) 80.0khz (note 16) fr fr fr 0.2 0.3 1.0 db db db notes: 14. the passband and stopband frequencies scale with fs. for example, 21.8khz at ?0.1db is 0.454 x fs. the reference frequency of these responses is 1khz. 15. the calculating delay time which occurred by digital filtering. this time is from setting the input of analog signal to setting the 24bit data of both channels to the output register for adc. for dac, this time is from setting the 20/24bit data of both channels on input register to the output of analog signal. 16. 40khz; fs=96khz, 80khz; fs=192khz
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 12 - dc characteristics (ta=25 c; avdd, dvdd, pvdd=4.5 5.5v; tvdd=2.7 5.5v) parameter symbol min typ max units high-level input voltage (except xti pin) (xti pin) low-level input voltage (except xti pin) (xti pin) vih vih vil vil 2.2 70%dvdd - - - - - - - - 0.8 30%dvdd v v v v input voltage at ac coupling (xti pin) (note17) vac 40%dvdd - - vpp high-level output voltage (except tx0-1, dzf pins : iout=-400 a) (tx0-1 pin : iout=-400 a) (dzf pin : iout=-400 a) low-level output voltage (iout=400 a) voh voh voh vol tvdd-0.4 dvdd-0.4 avdd-0.4 - - - - - - - - 0.4 v v v v tx output voltage levels (figure 25) voh 0.4 0.5 0.6 v input leakage current iin - - 10 a notes: 17. in case of connecting capacitance to xti pin (refer to figure 4). s/pdif receiver characteristics (ta=25 c; avdd, dvdd=2.7~3.6v; tvdd=2.7~5.5v) parameter symbol min typ max units input resistance zin 10 k ? input voltage (internally biased at pvdd/2) vth 200 mvpp input hysteresis vhy - 50 mv input sample frequency fs 32 - 192 khz
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 13 - switching characteristics (adc/dac part) (ta=25 c; avdd, dvdd, pvdd=4.5 5.5v; tvdd=2.7 5.5v; c l =20pf) parameter symbol min typ max units master clock timing master clock 256fsn, 128fsd: pulse width low pulse width high 384fsn, 192fsd: pulse width low pulse width high 512fsn, 256fsd: pulse width low pulse width high fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh 8.192 27 27 12.288 20 20 16.384 15 15 12.288 18.432 24.576 mhz ns ns mhz ns ns mhz ns ns lrck1 timing (slave mode) tdm0= ?0?, tdm1= ?0? normal speed mode double speed mode quad speed mode duty cycle fsn fsd fsq duty 32 64 120 45 48 96 192 55 khz khz khz % tdm0= ?1?, tdm1= ?0? lrck1 frequency ?h? time ?l? time fsd tlrh tlrl 32 1/256fs 1/256fs 48 khz ns ns tdm0= ?1?, tdm1= ?1? lrck1 frequency ?h? time ?l? time fsd tlrh tlrl 64 1/128fs 1/128fs 96 khz ns ns lrck1 timing (master mode) tdm0= ?0?, tdm1= ?0? normal speed mode double speed mode quad speed mode duty cycle fsn fsd fsq duty 32 64 120 50 48 96 192 khz khz khz % tdm0= ?1?, tdm1= ?0? lrck1 frequency ?h? time (note 18) fsn tlrh 32 1/8fs 48 khz ns tdm0= ?1?, tdm1= ?1? lrck1 frequency ?h? time (note 18) fsd tlrh 64 1/4fs 96 khz ns power-down & reset timing pdn pulse width (note 19) pdn ? ? to sdto1 valid (note 20) tpd tpdv 150 522 ns 1/fs notes: 18. ?l? time at i 2 s format. 19. the AK4588 can be reset by bringing pdn ?l? to ?h? upon power-up. 20. these cycles are the number of lrck rising from pdn rising.
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 14 - parameter symbol min typ max units audio interface timing (slave mode) tdm0= ?0? , tdm1= ?0? bick1 period bick1 pulse width low pulse width high lrck1 edge to bick1 ? ? (note 21) bick1 ? ? to lrck1 edge (note 21) lrck1 to sdto1(msb) bick1 ? ? to sdto1 sdti1-4,daux1 hold time sdti1-4,daux1 setup time tbck tbckl tbckh tlrb tblr tlrs tbsd tsdh tsds 81 32 32 20 20 20 20 40 40 ns ns ns ns ns ns ns ns ns ns tdm0= ?1? , tdm1= ?1? bick1 period bick1 pulse width low pulse width high lrck1 edge to bick1 ? ? (note 21) bick1 ? ? to lrck1 edge (note 21) bick1 ? ? to sdto1 sdti1 hold time sdti1 setup time tbck tbckl tbckh tlrb tblr tbsd tsdh tsds 81 32 32 20 20 10 10 20 ns ns ns ns ns ns ns ns ns tdm0= ?1? , tdm1= ?1? bick1 period bick1 pulse width low pulse width high lrck1 edge to bick1 ? ? (note 21) bick1 ? ? to lrck1 edge (note 21) bick1 ? ? to sdto1 sdti1-2 hold time sdti1-2 setup time tbck tbckl tbckh tlrb tblr tbsd tsdh tsds 81 32 32 20 20 10 10 20 ns ns ns ns ns ns ns ns ns audio interface timing (master mode) tdm0= ?0? , tdm1= ?0? bick1 frequency bick1 duty bick1 ? ? to lrck1 edge bick1? ? to sdto1 sdti1-4,daux1 hold time sdti1-4,daux1 setup time fbck dbck tmblr tbsd tsdh tsds -20 20 20 64fs 50 20 40 hz % ns ns ns ns tdm0= ?1?, tdm1= ?0? bick1 frequency bick1 duty (note 22) bick1 ? ? to lrck1 edge bick1 ? ? to sdto1 sdti1 hold time sdti1 setup time fbck dbck tmblr tbsd tsdh tsds -12 10 10 256fs 50 12 20 hz % ns ns ns ns tdm0= ?1?, tdm1= ?1? bick1 frequency bick1 duty (note 23) bick1 ? ? to lrck1 edge bick1 ? ? to sdto1 sdti1-2 hold time sdti1-2 setup time fbck dbck tmblr tbsd tsdh tsds -12 10 10 128fs 50 12 20 hz % ns ns ns ns notes: 21. bick rising edge must not occur at the same time as lrck edge. 22. when mclk is 512fs dbck is guaranteed. when 384fs and 256fs, dbck can not be guaranteed. 23. when mclk is 256fs dbck is guaranteed. when 128fs, dbck can not be guaranteed.
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 15 - timing diagram(adc/dac part) 1/fclk tclkl vih tclkh mclk vil 1/fsn, 1/fsd lrck1 vih vil tbck tbckl vih tbckh bick1 vil clock timing (tdm0 = ?0?) 1/fclk tclkl vih tclkh mclk vil 1/fs lrck1 vih vil tlrl tlrh tbck tbckl vih tbckh bick1 vil clock timing (tdm0 = ?1?)
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 16 - tlrb lrck1 vih bick1 vil tlrs sdto1 50%tvdd tbsd vih vil tblr tsds sdti vih vil tsdh audio interface timing (tdm0 = ?0?) tlrb lrck1 vih bick1 vil sdto1 50%tvdd tbsd vih vil tblr tsds sdti vih vil tsdh audio interface timing (tdm0 = ?1?)
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 17 - lrck1 bick1 sdto1 tbsd tmblr 50%dvdd 50%dvdd 50%dvdd daux1 tdxh tdxs vih vil audio interface timing (master mode)
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 18 - switching characteristics (dir/dit part) (ta=25 c; dvdd, avdd4.5~5.5v, tvdd=2.7~5.5v; c l =20pf) parameter symbol min typ max units master clock timing crystal resonator frequency fxtal 11.2896 24.576 mhz external clock frequency duty feclk declk 11.2896 40 50 24.576 60 mhz % mcko1 output frequency duty fmck1 dmck1 4.096 40 50 24.576 60 mhz % mcko2 output frequency duty fmck2 dmck2 2.048 40 50 24.576 60 mhz % pll clock recover frequency (rx0-7) fpll 32 - 192 khz lrck2 frequency duty cycle fs dlck 32 45 192 55 khz % audio interface timing slave mode bick2 period bick2pulse width low pulse width high lrck2 edge to bick2 ? ? (note 24) bick2 ? ? to lrck2 edge (note 24) lrck2 to sdto2 (msb) bick2 ? ? to sdto2 daux2 hold time daux2 setup time tbck tbckl tbckh tlrb tblr tlrm tbsd tdxh tdxs 80 30 30 20 20 20 20 30 30 ns ns ns ns ns ns ns ns ns master mode bick2 frequency bick2 duty bick2 ? ? to lrck2 bick2 ? ? to sdto2 daux2 hold time daux2 setup time fbck dbck tmblr tbsd tdxh tdxs -20 20 20 64fs 50 20 15 hz % ns ns ns ns notes; 24. bick rising edge must not occur at the same time as lrck edge.
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 19 - timing diagram(dir/dit part) 1/feclk teclkl vih teclkh xti vil declk = teclkh x feclk x 100 = teclkl x feclk x 100 1/fmck1 50%dvdd mcko1 tmckl1 tmckh1 dmck1 = tmckh1 x fmck1 x 100 = tmckl1 x fmck1 x 100 1/fmck2 50%dvdd mcko2 tmckl2 tmckh2 dmck2 = tmckh2 x fmck2 x 100 = tmckl2 x fmck2 x 100 1/fs lrck1 vih vil tlrl tlrh dlck = tlrh x fs x 100 = tlrl x fs x 100 clock timing tlrb lrck1 bick1 sdto1 tbsd tblr tbckl tbckh tlrm 50%dvdd daux1 tdxs tdxh vih vil vih vil vih vil tbck serial interface timing (slave mode)
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 20 - lrck1 bick1 sdto1 tbsd tmblr 50%dvdd 50%dvdd 50%dvdd daux1 tdxh tdxs vih vil serial interface timing (master mode) tpw pdn vil power down & reset timing
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 21 - switching characteristics (adc/dac part and dir/dit part) (ta=25 purchase of asahi kasei microsystems co., ltd i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system, provided the system conform to the i 2 c specifications defined by philips.
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 22 - timing diagram (adc/dac part and dir/dit part) tcckl csn cclk tcds cdti tcdh tcss c0 a 4 tcckh cdto hi-z r/w c1 vih vil vih vil vih vil tcck write/read command input timing in 4-wire serial mode the adc/dac part doesn?t support read command. tcsw csn cclk cdti d2 d0 tcsh cdto hi-z d1 d3 vih vil vih vil vih vil write data input timing in 4-wire serial mode csn cclk tdcd cdto d7 d6 cdti a1 a0 d5 hi-z 50%dvdd vih vil vih vil vih vil read data output timing 1 in 4-wire serial mode the adc/dac part doesn?t support read command..
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 23 - csn cclk tccz cdto d2 d1 cdti d0 d3 tcsw tcsh 50%dvdd vih vil vih vil vih vil read data input timing 2 in 4-wire serial mode the adc/dac part doesn?t support read command. thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta sto p start start sto p tsu:sto vil vih vil tsp i 2 c bus mode timing the adc/dac part doesn?t support read command. tpd vil pdn tpdv sdto 50%tvdd vih power-down & reset timing
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 24 - operation overview (adc/dac part) system clock the external clocks, which are required to operate the AK4588, are mclk, lrck1 and bick1. mclk should be synchronized with lrck1 but the phase is not critical. there are two methods to set mclk frequency. in manual setting mode (acks bit = ?0?: default), the sampling speed is set by dfs1-0 bit (table 1). the frequency of mclk at each sampling speed is set automatically. (table 2, 3, 4) in auto setting mode (acks bit = ?1?), as mclk frequency is detected automatically (table 5) and the internal master clock becomes the appropriate frequency (table 6), it is not necessary to set dfs1-0 bits. only mclk is necessary in the master mode. master clock input frequency should be selected by cks1-0 bits, and sampling speed should be selected by dfs1-0 bits. the frequencies and the duties of the clocks (lrck, bick) may not be stabile after setting cks1-0 bits and dfs1-0 bits up. external clocks (mclk, bick1) should always be present whenever the AK4588 is in normal operation mode (pdn pin = ?h?). if these clocks are not provided, the AK4588 may draw excess current because the device utilizes dynamic refreshed logic internally. if the external clocks are not present, the AK4588 should be in the power-down mode (pdn pin = ?l?) or in the reset mode (rstn bit = ?0?). after exiting reset at power-up etc., the AK4588 is in the power-down mode until mclk and lrck are input. in the master mode, external clock(mclk) should always be supplied except in the power-down mode. it is in power-down mode until mclk will be supplied, when reset was canceled by power-on and so on. dfs1 dfs0 sampling speed (fs) 0 0 normal speed mode 32khz~48khz 0 1 double speed mode 64khz~96khz default 1 0 quad speed mode 120khz~192khz table 1. sampling speed (manual setting mode) cks1 cks0 normal double quad 0 0 256fs 128fs 128fs default 0 1 384fs 192fs 128fs 1 0 512fs 256fs 128fs 1 1 256fs 256fs 128fs table 2.master clock input select (master mode) lrck1 mclk (mhz) bick1 (mhz) fs 256fs 384fs 512fs 64fs 32.0khz 8.1920 12.2880 16.3840 2.0480 44.1khz 11.2896 16.9344 22.5792 2.8224 48.0khz 12.2880 18.4320 24.5760 3.0720 table 3. system clock example (normal speed mode @manual setting mode) lrck1 mclk (mhz) bick1 (mhz) fs 128fs 192fs 256fs 64fs 88.2khz 11.2896 16.9344 22.5792 5.6448 96.0khz 12.2880 18.4320 24.5760 6.1440 table 4. system clock example (double speed mode @manual setting mode) (note: at double speed mode(dfs1= ?0?, dfs0 = ?1?), 128fs and 192fs are not available for adc.)
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 25 - lrck1 mclk (mhz) bick1 (mhz) fs 128fs 192fs 256fs 64fs 176.4khz 22.5792 - - 11.2896 192.0khz 24.5760 - - 12.2880 table 5. system clock example (quad speed mode @manual setting mode) (note: at quad speed mode(dfs1= ?1?, dfs0 = ?0?) are not available for adc.) mclk sampling speed 512fs normal 256fs double 128fs quad table 6. sampling speed (auto setting mode) lrck1 mclk (mhz) fs 128fs 256fs 512fs sampling speed 32.0khz - - 16.3840 44.1khz - - 22.5792 48.0khz - - 24.5760 normal 88.2khz - 22.5792 - 96.0khz - 24.5760 - double 176.4khz 22.5792 - - 192.0khz 24.5760 - - quad table 7. system clock example (auto setting mode) de-emphasis filter the AK4588 includes the digital de-emphasis filter (tc=50/15 s) by iir filter. de-emphasis filter is not available in double speed mode and quad speed mode. this filter corresponds to three sampling frequencies (32khz, 44.1khz, 48khz). de-emphasis of each dac can be set individually by register data of dema1-c0 bits (dac1: dema1-0 bits, dac2: demb1-0 bits, dac3: demc1-0 bits, dac4: demd1-0 bits, see ?register definitions?). mode sampling speed dem1 dem0 dem 0 normal speed 0 0 44.1khz 1 normal speed 0 1 off 2 normal speed 1 0 48khz 3 normal speed 1 1 32khz default table 8. de-emphasis control digital high pass filter the adc has a digital high pass filter for dc offset cancel. the cut-off frequency of the hpf is 1.0hz at fs=48khz and scales with sampling rate (fs).
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 26 - master mode and slave mode master mode can be selected by setting master pin to ?h?. lrck1 and bick1 will be outputs in master mode. and, slave mode can be selected by setting this pin to ?l?. lrck1 and bick1 will be inputs in slave mode. operation of lrck1 and bick1 is shown below table 9. table 9. operation of lrck1 and bick1 audio serial interface format when tdm pin= ?l?, four modes can be selected by the dif1-0 bits as shown in table 9. in all modes the serial data is msb-first, 2?s compliment format. the sdto is clocked out on the falling edge of bick1 and the sdti/daux1 are latched on the rising edge of bick1. figures 1 4 shows the timing at sdos = ?l?. in this case, the sdto outputs the adc output data. when sdos bits = ?1?, the data input to daux1 is converted to sdto1?s format and output from sdto1. mode 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23 in sdti input formats can be used for 16-20bit data by zeroing the unused lsbs. lrck1 bick1 mode master tdm 1 tdm0 dif1 dif0 sdto1 sdti1-4, daux i/o i/ o 0 0 0 0 0 0 24bit, left justified 20bit, right justified h/l i 48fs i 1 0 0 0 0 1 24bit, left justified 24bit, right justified h/l i 48fs i 2 0 0 0 1 0 24bit, left justified 24bit, left justified h/l i 48fs i default 3 0 0 0 1 1 24bit, i 2 s 24bit, i 2 s l/h i 48fs i 4 1 0 0 0 0 24bit, left justified 20bit, right justified h/l o 64fs o 5 1 0 0 0 1 24bit, left justified 24bit, right justified h/l o 64fs o 6 1 0 0 1 0 24bit, left justified 24bit, left justified h/l o 64fs o 7 1 0 0 1 1 24bit, i 2 s 24bit, i 2 s l/h o 64fs o table 10. audio data formats (normal mode) the audio serial interface format becomes the tdm mode if tdm pin is set to ?h?. in the tdm 256 mode, the serial data of all dac (eight channels) is input to the sdti1 pin. the input data to sdti2-4 pins is ignored. bick1 should be fixed to 256fs. ?h? time and ?l? time of lrck1 pin should be 1/256fs at least. four modes can be selected by the dif1-0 bits was shown in table 10. in all modes the serial data is msb-first, 2?s compliment format. the sdto1 pin is clocked out on the falling edge of bick1 pin and the sdti1 pin are latched on the rising edge of bick1 pin. sdos bit and loop1-0 bits should be set to ?0? at the tdm mode. tdm 128 mode can be set by tdm1 bit. in double speed mode, the serial data of dac (four channels; l1, r1, l2, r2) is input to the sdti1 pin. other four data (l3, r3, l4, r4) are input to the sdti2 pin. tdm0 register should be set to ?h? if tdm 256 mode is selected. tdm0 register, tdm1 register should be set to ?h? if double speed mode is selected in tdm 128 mode. pdn pin pwadn bit, pwdan bit master pin lrck1 bick1 l input input l -- h ?l? output ?l? output l input input h 00 h ?l? output ?l? output l input input h except for 00 h output output
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 27 - lrck1 bick1 mode master tdm 1 tdm0 dif1 dif0 sdto1 sdti1 i/o i/o 8 0 0 1 0 0 24bit, left justified 20bit, right justified i 256fs i 9 0 0 1 0 1 24bit, left justified 24bit, right justified i 256fs i 10 0 0 1 1 0 24bit, left justified 24bit, left justified i 256fs i 11 0 0 1 1 1 24bit, i 2 s 24bit, i 2 s i 256fs i 12 1 0 1 0 0 24bit, left justified 20bit, right justified o 256fs o 13 1 0 1 0 1 24bit, left justified 24bit, right justified o 256fs o 14 1 0 1 1 0 24bit, left justified 24bit, left justified o 256fs o 15 1 0 1 1 1 24bit, i 2 s 24bit, i 2 s o 256fs o table 11. audio data formats (tdm 256 mode) lrck1 bick1 mode master tdm 1 tdm 0 dif1 dif0 sdto1 sdti1, sdti2 i/ o i/o 16 0 1 1 0 0 24bit, left justified 20bit, right justified i 128fs i 17 0 1 1 0 1 24bit, left justified 24bit, right justified i 128fs i 18 0 1 1 1 0 24bit, left justified 24bit, left justified i 128fs i 19 0 1 1 1 1 24bit, i 2 s 24bit, i 2 s i 128fs i 20 1 1 1 0 0 24bit, left justified 20bit, right justified o 128fs o 21 1 1 1 0 1 24bit, left justified 24bit, right justified o 128fs o 22 1 1 1 1 0 24bit, left justified 24bit, left justified o 128fs o 23 1 1 1 1 1 24bit, i 2 s 24bit, i 2 s o 128fs o table 12. audio data formats (tdm 128 mode)
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 28 - lrck1 bick1 ( 64fs ) sdto1 ( o ) 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 23 1 22 0 23 22 12 11 10 0 23 sdti ( i ) 1 18 0 19 8 7 1 18 0 19 8 7 lch data rch data don?t care don?t care 12 11 10 sdto-23:msb, 0:lsb; sdti-19:msb, 0:lsb figure 1. mode 0,4 timing lrck1 bick1 ( 64fs ) sdto1 ( o ) 0 1 2 8 9 10 24 25 31 0 1 2 8 9 10 24 25 31 0 23 1 22 0 23 22 16 15 14 0 23 sdti ( i ) 1 22 0 23 8 7 1 22 0 23 8 7 23:msb, 0:lsb lch data rch data don?t care don?t care 16 15 14 figure 2. mode 1 ,5 timing lrck1 bick1 ( 64fs ) sdto1 ( o ) 0 1 2 21 22 23 24 31 0 1 2 0 23 1 22 1 23 22 23 sdti(i) 22 23 0 22 23 23:msb, 0:lsb lch data rch data don?t care 2 2 1 28 29 30 23 0 22 23 24 31 1 0 don?t care 2 21 28 29 30 0 figure 3.mode 2,6 timing lrck1 bick1 ( 64fs ) sdto1 ( o ) 0 1 2 3 22 23 24 25 0 0 1 sdti ( i ) 31 29 30 23 22 1 22 23 0 23:msb, 0:lsb lch data rch data don?t care 2 2 1 0 2 3 22 23 24 25 0 31 29 30 23 22 1 22 23 0 don?t care 2 21 0 1 figure 4. mode 3 ,7 timing
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 29 - 256 bick bick1(256fs) sdto1(o) sdti1(i) 22 0 lch 32 bick 18 0 l1 32 bick 18 0 r1 32 bick 18 0 l2 32 bick 18 0 r2 32 bick 18 0 l3 32 bick 18 0 r3 32 bick 18 0 l4 32 bick 18 0 r4 32 bick 22 0 rch 32 bick 22 23 19 19 19 19 19 23 19 19 19 23 19 lrck1 lrck1 (mode 8) (mode 12) figure 5. mode 8 ,12 timing 256 bick bick1(256fs) sdto1(o) sdti1(i) 22 0 lch 32 bick 22 0 l1 32 bick 22 0 r1 32 bick 22 0 l2 32 bick 22 0 r2 32 bick 22 0 l3 32 bick 22 0 r3 32 bick 22 0 l4 32 bick 22 0 r4 32 bick 22 0 rch 32 bick 22 23 23 23 23 23 23 23 23 23 23 23 23 lrck1 lrck1 (mode 9) (mode 13) figure 6. mode 9 ,13 timing 256 bick bick1(256fs) sdto1(o) sdti1(i) 22 0 lch 32 bick 22 0 l1 32 bick 22 0 r1 32 bick 22 0 l2 32 bick 22 0 r2 32 bick 22 0 l3 32 bick 22 0 r3 32 bick 22 0 l4 32 bick 22 0 r4 32 bick 22 0 rch 32 bick 22 22 23 23 23 23 23 23 23 23 23 23 23 23 lrck1 lrck1 (mode 10) (mode 14) figure 7. mode 10 ,14 timinig 256 bick bick1(256fs) sdto1(o) sdti1(i) 23 0 lch 32 bick 23 0 l1 32 bick 23 0 r1 32 bick 23 0 l2 32 bick 23 0 r2 32 bick 23 0 l3 32 bick 23 0 r3 32 bick 23 0 l4 32 bick 23 0 r4 32 bick 23 0 rch 32 bick 23 23 lrck1 lrck1 (mode 11) (mode 15) figure 8. mode 11 ,15 timing
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 30 - 128 bick bick1(128fs) sdto1(o) 22 0 lch 32 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick l4 32 bick r4 32 bick 22 0 rch 32 bick 22 23 23 23 sdti1(i) 18 0 18 0 18 0 18 0 19 19 19 19 19 lrck1 sdti2(i) 18 0 18 0 18 0 18 0 19 19 19 19 19 lrck1 (mode 16) (mode 20) figure 9. mode 16 ,20 timing 128 bick bick1(128fs) (mode 17) 22 0 lch 32 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick l4 32 bick r4 32 bick 22 0 rch 32 bick 22 23 23 23 sdti1(i) 22 0 22 0 22 0 22 0 23 23 23 23 19 lrck1 sdti2(i) 22 0 22 0 22 0 22 0 23 23 23 23 19 lrck1 (mode 21) figure 10. mode 17 ,21 timing 128 bick bick1(128fs) sdto1(o) 22 0 lch 32 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick l4 32 bick r4 32 bick 22 0 rch 32 bick 22 23 23 23 lrck1 sdti1(i) 22 0 22 0 22 0 22 0 23 23 23 23 22 23 sdti2(i) 22 0 22 0 22 0 22 0 23 23 23 23 22 23 lrck1 (mode 18) (mode 22) figure 11. mode 18 ,22 timing
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 31 - 128 bick bick1(128fs) sdto1(o) 22 0 lch 32 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick l3 32 bick r3 32 bick l4 32 bick r4 32 bick 22 0 rch 32 bick 23 23 23 sdti1(i) 22 0 22 0 22 0 22 0 23 23 23 23 23 sdti2(i) 22 0 22 0 22 0 22 0 23 23 23 23 23 lrck1 lrck1 (mode 19) (mode 23) figure 12. mode 19 ,23 timing
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 32 - overflow detection the AK4588 has overflow detect function for analog input. overflow detect function is enable if ovfe bit is set to ?1? at serial control mode. ovf pin goes to ?h? if analog input of lch or rch overflows (more than -0.3dbfs). ovf output for overflowed analog input has the same group delay as adc (gd = 19.1/fs = 398 s @fs=48khz). ovf is ?l? for 522/fs (=11.8ms @fs=48khz) after pdn = ? ?, and then overflow detection is enabled. zero detection the AK4588 has two pins for zero detect flag outputs. channel grouping can be selected by dzfm3-0 bits if p/s = ?l? and dzfe = ?l? (table 13). dzf1 pin corresponds to the group 1 channels and dzf2 pin corresponds to the group 2 channels. however dzf2 pin becomes ovf pin if ovfe bit is set to ?1?. zero detection mode is set to mode 0 if dzfe= ?h? regardless of p/s pin. dzf1 is and of all eight channels and dzf2 is disabled (?l?) at mode 0. table 12 shows the relation of p/s, dzfe, ovfe and dzf. when the input data of all channels in the group 1(group 2) are continuously zeros for 8192 lrck1 cycles, dzf1(dzf2) pin goes to ?h?. dzf1(dzf2) pin immediately goes to ?l? if input data of any channels in the group 1(group 2) is not zero after going dzf1(dzf2) ?h?. dzfm aout mode 3 2 1 0 l1 r1 l2 r2 l3 r3 l4 r4 0 0 0 0 0 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 1 0 0 0 1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf2 dzf2 dzf2 2 0 0 1 0 dzf1 dzf1 dzf1 dzf1 dzf2 dzf2 dzf2 dzf2 3 0 0 1 1 dzf1 dzf1 dzf1 dzf2 dzf2 dzf2 dzf2 dzf2 4 0 1 0 0 dzf1 dzf1 dzf2 dzf2 dzf2 dzf2 dzf2 dzf2 5 0 1 0 1 dzf1 dzf2 dzf2 dzf2 dzf2 dzf2 dzf2 dzf2 6 0 1 1 0 dzf2 dzf2 dzf2 dzf2 dzf2 dzf2 dzf2 dzf2 7 0 1 1 1 disable (dzf1=dzf2 = ?l?) 8 1 0 0 0 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf2 9 1 0 0 1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf1 dzf2 dzf2 10 1 0 1 0 11 1 0 1 1 12 1 1 0 0 13 1 1 0 1 14 1 1 1 0 15 1 1 1 1 disable (dzf1=dzf2 = ?l?) default table 13. zero detect control ovfe bit dzf mode dzf1 pin dzf2/ovf pin ?0? selectable selectable selectable ?1? selectable selectable ovf output table 14. dzf1-2 pins outputs
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 33 - digital attenuator AK4588 has channel-independent digital attenuator (128 levels, 0.5db step). attenuation level of each channel can be set by each att7-0 bits (table 15). att7-0 attenuation level 00h 0db 01h -0.5db 02h -1.0db : : 7dh -62.5db 7eh -63db 7fh mute (- ) : feh mute (- ) ffh mute (- ) default table 15. attenuation level of digital attenuator transition time between set values of att7-0 bits can be selected by ats1-0 bits (table 16). transition between set values is the soft transition. therefore, the switching noise does not occur in the transition. mode ats1 ats0 att speed 0 0 0 1792/fs 1 0 1 896/fs 2 1 0 256/fs 3 1 1 256/fs default table 16. transition time between set values of att7-0 bits the transition between set values is soft transition of 1792 levels in mode 0. it takes 1792/fs (37.3ms@fs=48khz) from 00h(0db) to 7fh(mute) in mode 0. if pdn pin goes to ?l?, the atts are initialized to 00h. the atts are 00h when rstn = ?0?. when rstn return to ?1?, the atts fade to their current value.
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 34 - soft mute operation soft mute operation is performed at digital domain. when the smute bit goes to ?1?, the output signal is attenuated by - during att_data att transition time (table 16) from the current att level. when the smute bit is returned to ?0?, the mute is cancelled and the output attenuation gradually changes to the att level during att_data att transition time. if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to att level by the same cycle. the soft mute is effective for changing the signal source without stopping the signal transmission. smute bit attenuation dzf1,2 att level - aout 8192/fs gd gd (1) (2) (3) (4) (1) notes: (1) att_data att transition time (table 16). for example, in normal speed mode, this time is 1792lrck1 cycles (1792/fs) at att_data=00h. att transition of the soft-mute is from 00h to 7fh (2) the analog output corresponding to the digital input has a group delay, gd. (3) if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to att level by the same cycle. (4) when the input data at all the channels of the group are continuously zeros for 8192 lrck1 cycles, dzf pin of each channel goes to ?h?. dzf pin immediately goes to ?l? if the input data of either channel of the group are not zero after going dzf ?h?. figure 13. soft mute and zero detection system reset the AK4588 should be reset once by bringing pdn pin = ?l? upon power-up. the ak 4588 is powered up and the internal timing starts clocking by lrck1 ? ? after exiting reset and power down state by mclk. the AK4588 is in the power-down mode until mclk and lrck1 are input.
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 35 - power on/off sequence the adc and dacs of AK4588 are pl aced in the power-down mode by bringing pdn pin ?l? and both digital filters are reset at the same time. pdn pin ?l? also reset the control registers to their default values. in the power-down mode, the analog outputs go to vcom voltage and dzf1-2 pins go to ?l?. this reset should always be done after power-up. in case of the adc, an analog initialization cycle starts after exiting the power-down mode. therefore, the output data, sdto1 becomes available after 522 cycles of lrck1 clock. in case of the dac, an analog initialization cycle starts after exiting the power-down mode. the analog outputs are vcom voltage during the initialization. figure 14 shows the sequences of the power-down and the power-up. the adc and all dacs can be powered-down individually by pwadn and pwdan bits. and dac1-4 can be power-down individually by pd1-4 bits. in this case, the internal register values are not initialized. when pwadn bit = ?0?, sdto1 pin goes to ?l?. when pwdan bit = ?0? and pd1-4 bits = ?0?, the analog outputs go to vcom voltage and dzf1-2 pins go to ?h?. because some click noise occurs, the analog output should muted externally if the click noise influences system application. adc internal state pdn clock in mclk,lrck, sclk adc in (analog) adc out (digital) dac internal state dac in (digital) dac out (analog) external mute mute on (9) dzf1/dzf2 power power-down don?t care gd ?0?data power-down ?0?data gd (3) (3) (4) (6) (7) (8) 522/fs init cycle normal operation (1) gd normal operation gd (5) (6) 516/fs init cycle (2) 10 11/fs (10) mute on ?0?data ?0?data don?t care
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 36 - notes: (1) the analog part of adc is initialized after exiting the power-down state. (2) the analog part of dac is initialized after exiting the power-down state. (3) digital output corresponding to analog input and analog output corresponding to digital input have the group delay (gd). (4) adc output is ?0? data at the power-down state. (5) click noise occurs at the end of initialization of the analog part. please mute the digital output externally if the click noise influences system application. (6) click noise occurs at the falling edge of pdn and at 512/fs after the rising edge of pdn. (7) when the external clocks (mclk, bick1 and lrck1) are stopped, the AK4588 should be in the power-down mode. (8) dzf pins are ?l? in the power-down mode (pdn pin = ?l?). (9) please mute the analog output externally if the click noise (6) influences system application. (10) dzf= ?l? for 10 11/fs after pdn= ? ?. figure 14. power-down/up sequence example
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 37 - reset function when rstn bit = ?0?, adc and dacs are powered-down but the internal register are not initialized. the analog outputs go to vcom voltage, dzf1-2 pins go to ?h? and sdto1 pin goes to ?l?. because some click noise occurs, the analog output should muted externally if the click noise influences system application. figure 15 shows the power-up sequence. adc internal state rstn bit normal operation digital block power-down normal operation don?t care gd gd clock in mclk,lrck,sclk adc in (analog) ?0?data adc out (digital) normal operation normal operation dac internal state ?0?data dac in (digital) dac out (analog) gd gd (2) (2) (3) (4) (6) (6) dzf1/dzf2 (7) internal rstn bit digital block power-down 1~2/fs (9) 4~5/fs (9) 4 5/fs (8) (5) 516/fs init cycle (1) notes: (1) the analog part of adc is initialized after exiting the reset state. (2) digital output corresponding to analog input and analog output corresponding to digital input have the group delay (gd). (3) adc output is ?0? data at the power-down state. (4) click noise occurs when the internal rstn bit becomes ?1?. please mute the digital output externally if the click noise influences system application. (5) the analog outputs go to vcom voltage. (6) click noise occurs at 4 5/fs after rstn bit becomes ?0?, and occurs at 1 2/fs after rstn bit becomes ?1?. this noise is output even if ?0? data is input. (7) the external clocks (mclk, bick1 and lrck1) can be stopped in the reset mode. when exiting the reset mode, ?1? should be written to rstn bit after the external clocks (mclk, bick1 and lrck1) are fed. (8) dzf pins go to ?h? when the rstn bit becomes ?0?, and go to ?l? at 6~7/fs after rstn bit becomes ?1?. (9) there is a delay, 4~5/fs from rstn bit ?0? to the internal rstn bit ?0?. figure 15. reset sequence example
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 38 - dac partial power-down function all dacs of AK4588 can be powered-down individually by pd1-4 bits. the analog part of dac is in power-down by pd1-4 bits =?1?, however, the digital part is not in power-down by it. even if all dacs were set in power-down by the partial power-down bits, the digital part continue to function. the analog output of the channel which is set in power-down by pd1-4 bits is fixed to the voltage of vcom. and though dzf detection is being done, the result of dzf detection stops reflecting to dzf1-2 pins. because some click noise occurs in both set-up and release of power-down, either the analog output should be muted externally or pd1-4 bits should be set up when it is in pwdan bit =?0? or rstn bit =?0?, if the click noise influences system application. figure 16 shows the sequence of the power-down and the power-up by pd1-4 bits. pd1-4 bit dzf1/dzf2 8192/fs ?0?data dac in (digital) dac out (analog) gd gd (1) (3) (3) (2) dac digital internal state normal operation normal operation dac analog internal state power-down normal operation clock in mclk,lrck,sclk dac in (digital) dac out (analog) normal operation channel (4) (5) gd 8192/fs gd power-down normal operation normal operation (2) (3) (3) (4) power down channel dzf detect internal state dzf detect internal state ?0?data (6) notes: (1) digital output corresponding to analog input and analog output corresponding to digital input have the group delay (gd). (2) analog output of the dac powered down by pd1-4 bits =?1? is fixed to the voltage of vcom. (3) immediately after pd1-4 bits are changed, some click noise occurs at the output of the channel changed by the own pd bits. (4) though dzf detection is being done at a certain channel which set up pd1-4 bits =?1?, the result of dzf detection stops reflecting to dzf1-2 pins. (5) dzf detection of the dac which is set up by the power-down setting is ignored, and dzf1-2 pins become ?h?. (6) when the power-down function is set up and the channel has input signal, even if the partial power-down function is set up, dzf1-2 bits do not become ?h?. figure 16. dac partial power-down example
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 39 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 0 0 tdm1 tdm0 dif1 dif0 0 smute 01h control 2 cks1 dfs1 loop1 loop0 sdos dfs0 acks cks0 02h lout1 volume control att7 att6 att5 att4 att3 att2 att1 att0 03h rout1 volume control att7 att6 att5 att4 att3 att2 att1 att0 04h lout2 volume control att7 att6 att5 att4 att3 att2 att1 att0 05h rout2 volume control att7 att6 att5 att4 att3 att2 att1 att0 06h lout3 volume control att7 att6 att5 att4 att3 att2 att1 att0 07h rout3 volume control att7 att6 att5 att4 att3 att2 att1 att0 08h de-emphasis demd1 demd0 dema1 dema0 demb1 demb0 demc1 demc0 09h att speed & power down control 0 pd4 ats1 ats0 pd3 pd2 pd1 rstn 0ah zero detect ovfe dzfm3 dzfm2 dzfm1 dzfm0 pwvrn pwadn pwdan 0bh lout4 volume control att7 att6 att5 att4 att3 att2 att1 att0 0ch rout4 volume control att7 att6 att5 att4 att3 att2 att1 att0 note: for addresses from 0dh to 1fh, data is not written. when pdn pin goes to ?l?, the registers are initialized to their default values. when rstn bit goes to ?0?, the internal timing is reset and dzf1-2 pins go to ?h?, but registers are not initialized to their default values.
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 40 - register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 0 0 tdm1 tdm0 dif1 dif0 0 smut e default 0 0 0 0 1 0 0 0 smute: soft mute enable 0: normal operation 1: all dac outputs soft-muted dif1-0: audio data interface modes (see table 10) initial: ?10?, mode 2 tdm1-0: tdm format select (see table 11,12) mode tdm1 tdm0 sdti sampling speed 0 0 0 1-4 normal, double, four times speed 1 0 1 1 normal speed 2 1 1 1-2 normal, double speed
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 41 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h control 2 cks1 dfs1 loop1 loop0 sdos dfs0 acks cks0 default 0 0 0 0 0 0 0 0 acks: master clock frequency auto setting mode enable 0: disable, manual setting mode 1: enable, auto setting mode master clock frequency is detected automatically at acks bit ?1?. in this case, the setting of dfs1-0 bits are ignored. when this bit is ?0?, dfs1-0 bits set the sampling speed mode. dfs1-0: sampling speed mode (see table 1.) the setting of dfs1-0 bits are ignored at acks bit ?1?. cks0-1: master clock frequency select (see table 2.) sdos: sdto1 source select 0: adc 1: daux sdos bit should be set to ?0? at tdm bit ?1?. in the case of pwadn bit =?0? and pwdan bit =?0?, the setting of sdos bit becomes invalid. and adc is selected. the output of sdto1 becomes ?l? at pwadn bit =?0?. loop1-0: loopback mode enable 00: normal (no loop back) 01: lin lout1, lout2, lout3, lout4 rin rout1, rout2, rout3, rout4 the digital adc output (daux1 input if sdos = ?1?) is connected to the digital dac input. in this mode, the input dac data to sdti1-3 is ignored. the audio format of sdto1 at loopback mode becomes mode 2 at mode 0, and mode 3 at mode 1, respectively. 10: sdti1(l) sdti2(l), sdti3(l), sdti4(l) sdti1(r) sdti2(r), sdti3(r), sdti4(r) in this mode the input dac data to sdti2-4 is ignored. 11: n/a loop1-0 bits should be set to ?00? at tdm bit ?1?. in the case of pwadn bit =?0? and pwdan bit =?0?, the setting of loop1-0 bits become invalid. and adc is selected. and it becomes the normal operation (no loop back).
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 42 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h lout1 volume control att7 att6 att5 att4 att3 att2 att1 att0 03h rout1 volume control att7 att6 att5 att4 att3 att2 att1 att0 04h lout2 volume control att7 att6 att5 att4 att3 att2 att1 att0 05h rout2 volume control att7 att6 att5 att4 att3 att2 att1 att0 06h lout3 volume control att7 att6 att5 att4 att3 att2 att1 att0 07h rout3 volume control att7 att6 att5 att4 att3 att2 att1 att0 0bh lout4 volume control att7 att6 att5 att4 att3 att2 att1 att0 0ch rout4 volume control att7 att6 att5 att4 att3 att2 att1 att0 default 0 0 0 0 0 0 0 0 att7-0: attenuation level (see table 15.) addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h de-emphasis demd1 demd 0 dema 1 dema 0 demb 1 demb 0 demc 1 demc 0 default 0 1 0 1 0 1 0 1 dema1-0: de-emphasis response control for dac1 data on sdti1 (see table 8.) initial: ?01?, off demb1-0: de-emphasis response control for dac2 data on sdti2 (see table 8.) initial: ?01?, off demc1-0: de-emphasis response control for dac3 data on sdti3 (see table 8.) initial: ?01?, off demd1-0: de-emphasis response control for dac4 data on sdti4 (see table 8.) initial: ?01?, off
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 43 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h att speed & power down control 0 pd4 ats1 ats0 pd3 pd2 pd1 rstn default 0 0 0 0 0 0 0 1 rstn: internal timing reset 0: reset. dzf1-2 pins go to ?h?, but registers are not initialized. 1: normal operation ats1-0: digital attenuator transition time setting (see table 16.) initial: ?00?, mode 0 pd1-0: power-down control (0: power-up, 1: power-down) pd1: power down control of dac1 pd2: power down control of dac2 pd3: power down control of dac3 pd4: power down control of dac4 addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah zero detect ovfe dzfm3 dzfm2 dzfm1 dzfm0 pwvrn pwadn pwdan default 0 0 1 1 1 1 1 1 pwdan: power-down control of dac1-4 0: power-down 1: normal operation pwadn: power-down control of adc 0: power-down 1: normal operation pwvrn: power-down control of reference voltage 0: power-down 1: normal operation dzfm3-0: zero detect mode select (see table 13.) initial: ?0111?, disable ovfe: overflow detection enable 0: disable, pin#33 becomes dzf2 pin. 1: enable, pin#33 becomes ovf pin.
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 44 - operation overview (dir/dit part) non-pcm (ac-3, mpeg, etc.) and dts-cd bitstream detection the AK4588 has a non-pcm steam auto-detection function. when the 32bit mode non-pcm preamble based on dolby ?ac-3 data stream in iec60958 interface? is detected, the auto bit goes ?1?. the 96bit sync code consists of 0x0000, 0x0000, 0x0000, 0x0000, 0xf872 and 0x4e1f. detection of this pattern will set the auto bit ?1?. once the auto bit is set ?1?, it will remain ?1? until 4096 frames pass through the chip without additional sync pattern being detected. when those preambles are detected, the burst preambles pc and pd that follow those sync codes are stored to registers. the AK4588 also has the dts-cd bitstream auto-detection function. when AK45884 detects dts-cd bitstreams, dtscd bit goes to ?1?. when the next sync code does not come within 4096 flames, dtscd bit goes to ?0? until when ak4114 detects the stream again. 192khz clock recovery on chip low jitter pll has a wide lock range with 32khz to 192khz and the lock time is less than 20ms. the AK4588 has the sampling frequency detect function. by either the clock comparison against x?tal oscillator or using the channel status, AK4588 detects the sampling frequency (32khz, 44.1khz, 48khz, 88.2khz, 96khz, 176.4khz and 192khz). the pll loses lock when the received sync interval is incorrect. master clock the AK4588 has two clock outputs, mcko1 and mcko2. these clocks are derived from either the recovered clock or from the x'tal oscillator. the frequencies of the master clock outputs (mcko1 and mcko2) are set by ocks0 and ocks1 as shown in table 17. the 512fs clock will not output when 96khz and 192khz. the 256fs clock will not output when 192khz. no. ocks1 ocks0 mcko1 mcko2 x?tal fs (max) 0 0 0 256fs 256fs 256fs 96 khz 1 0 1 256fs 128fs 256fs 96 khz 2 1 0 512fs 256fs 512fs 48 khz 3 1 1 128fs 64fs 128fs 192 khz default table 17. master clock frequency select (stereo mode) clock operation mode the cm0/cm1 pins (or bits) select the clock source and the data source of sdto. in mode 2, the clock source is switched from pll to x'tal when pll goes unlock state. in mode3, the clock source is fixed to x'tal, but pll is also operating and the recovered data such as c bits can be monitored. for mode2 and 3, it is recommended that the frequency of x?tal is different from the recovered frequency from pll. mode cm1 cm0 unlock pll x'tal clock source sdto 0 0 0 - on on(note) pll rx 1 0 1 - off on x'tal daux 0 on on pll rx 2 1 0 1 on on x'tal daux 3 1 1 - on on x'tal daux default on: oscillation (power-up), off: stop (power-down) note : when the x?tal is not used as clock comparison for fs detection (i.e. xtl1,0= ?1,1?), the x?tal is off. table 18. clock operation mode select
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 45 - clock source the following circuits are available to feed the clock to xti pin of AK4588. 1) x?tal xti xto AK4588 25k ? c c figure 17. x?tal mode note: external capacitance depends on the crystal oscillator (typ. 10-40pf) 2) external clock xti xto AK4588 25k ? external clock xti xto AK4588 25k ? external clock c figure 18. (a).external clock mode figure 19. (b). external clock mode (input :cmos level) (input : 40%dvdd) - note: input clock must not exceed dvdd. 3) fixed to the clock operation mode 0 xti xto AK4588 25k ? figure 20. off mode
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 46 - sampling frequency and pre-emphasis detection the AK4588 has two methods for detecting the sampling frequency as follows. 1. clock comparison between recovered clock and x?tal oscillator 2. sampling frequency information on channel status those could be selected by xtl1, 0 bits. and the detected frequency is reported on fs3-0 bits. xtl1 xtl0 x?tal frequency 0 0 11.2896mhz 0 1 12.288mhz 1 0 24.576mhz 1 1 (use channel status) default table 19. reference x?tal frequency except xtl1,0= ?1,1? xtl1,0= ?1,1? register output fs consumer mode (note 2) professional mode fs3 fs2 fs1 fs0 clock comparison (note 1) byte3 bit3,2,1,0 byte0 bit7,6 byte4 bit6,5,4,3 0 0 0 0 44.1khz 44.1khz 0 0 0 0 0 1 0 0 0 0 0 0 0 1 reserved reserved 0 0 0 1 (others) 0 0 1 0 48khz 48khz 0 0 1 0 1 0 0 0 0 0 0 0 1 1 32khz 32khz 0 0 1 1 1 1 0 0 0 0 1 0 0 0 88.2khz 88.2khz ( 1 0 0 0 ) 0 0 1 0 1 0 1 0 1 0 96khz 96khz ( 1 0 1 0 ) 0 0 0 0 1 0 1 1 0 0 176.4khz 176.4khz ( 1 1 0 0 ) 0 0 1 0 1 1 1 1 1 0 192khz 192khz ( 1 1 1 0 ) 0 0 0 0 1 1 note1: at least 3% range is identified as the value in the table 20. in case of intermediate frequency of those two, fs3-0 bits indicate nearer value. when the frequency is much bigger than 192khz or much smaller than 32khz, fs3-0 bits may indicate ?0001?. note2: when consumer mode, byte3 bit3-0 are copied to fs3-0 bits. table 20. fs information the pre-emphasis information is detected and reported on pem bit. these information are extracted from channel 1 at default. it can be switched to channel 2 by cs12 bit in control register. pem pre-emphasis byte 0 bits 3-5 0 off 0x100 1 on 0x100 table 21. pem in consumer mode pem pre-emphasis byte 0 bits 2-4 0 off 110 1 on 110 table 22. pem in professional mode
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 47 - de-emphasis filter control the AK4588 includes the digital de-emphasis filter (tc=50/15s) by iir filter corresponding to four sampling frequencies (32khz, 44.1khz, 48khz and 96khz). when deau bit=?1?, the de-emphasis filter is enabled automatically by sampling frequency and pre-emphasis information in the channel status. the AK4588 goes this mode at default. therefore, in parallel mode, the AK4588 is always placed in this mode and the status bits in channel 1 control the de-emphasis filter. in serial mode, dem0/1 and dfs bits can control the de-emphasis filter when deau bit is ?0?. the internal de-emphasis filter is bypassed and the recovered data is output without any change if either pre-emphasis or de-emphasis mode is off. pem fs3 fs2 fs1 fs0 mode 1 0 0 0 0 44.1khz 1 0 0 1 0 48khz 1 0 0 1 1 32khz 1 1 0 1 0 96khz 1 (others) off 0 x x x x off table 23. de-emphasis auto control at deau bit = ?1? (default) pem dfs dem1 dem0 mode 1 0 0 0 44.1khz 1 0 0 1 off default 1 0 1 0 48khz 1 0 1 1 32khz 1 1 0 0 off 1 1 0 1 off 1 1 1 0 96khz 1 1 1 1 off 0 x x x off table 24. de-emphasis manual control at deau bit = ?0? system reset and power-down the AK4588 has a power-down mode for all circuits by pdn pin can be partially powerd-down by pwn bit. the rstn bit initializes the register and resets the internal timing. in parallel mode, only the control by pdn pin is enabled. the AK4588 should be reset once by bringing pdn pin = ?l? upon power-up. pdn pin: all analog and digital circuit are placed in the power-down and reset mode by bringing pdn pin = ?l?. all the registers are initialized, and clocks are stopped. reading/witting to the register are disabled. rstn bit (address 00h; d0): all the registers except pwn and rstn bits are initialized by bringing rstn bit = ?0?. the internal timings are also initialized. witting to the register is not available except pwn and rstn bits. reading to the register is disabled. pwn bit (address 00h; d1): the clock recovery part is initialized by bringing pwn bit = ?0?. in this case, clocks are stopped. the registers are not initialized and the mode settings are kept. writing and reading to the registers are enabled.
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 48 - biphase input and through output eight receiver inputs (rx0-7) are available in serial control mode. each input includes amplifier corresponding to unbalance mode and can accept the signal of 200mv or more. ips2-0 bits selects the r eceiver channel. when bcu bit = ?1?, the block start signal, c bit and u bit can output from each pins. ips2 ips1 ips0 input data 0 0 0 rx0 default 0 0 1 rx1 0 1 0 rx2 0 1 1 rx3 1 0 0 rx4 1 0 1 rx5 1 1 0 rx6 1 1 1 rx7 table 25. recovery data select b cout (or u,v) lrck (except i 2 s) c(l0) c(r0) c(l1) c(r31) c(l31) c(l32) c(r191) 1/4fs sdto l191 r191 l30 l31 r30 l0 r190 lrck (except i 2 s) sdto (except i 2 s) l30 r190 (mono mode) (normal mode) l191 r191 l0 r30 l31 lrck (i 2 s) lrck (i 2 s) figure 21. b, c, u, v output/input timings
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 49 - biphase output the AK4588 can output either the thr ough output(from dir) or transmitter output(dit; the data from daux2 is transformed to iec60958 format.) from tx1/0 pins. those could be selected by dit bit. the source of the through output from tx0 could be selected among rx0-8 by ops00,01 and 02 bits, for tx1, by ops10,11 and 12 bits respectively. when output daux2 data, v bit could be controlled by vin pin and first 5 bytes of c bit could be controlled by ct39-ct0 bits in control registers. when bit0= ?0?(consumer mode), bit20-23 (audio channel) could not be controlled directly but be controlled by ct20 bit. when the ct20 bit is ?1?, AK4588 outputs ?1000? as c20-23 for left channel and output ?0100? at c20-23 for right channel automatically. when ct20 bit is ?0?, AK4588 outputs ?0000? set as ?1000? for sub frame 1, and ?0100? for sub frame 2. u bits are fixed to ?0?.as c20-23 for both channel. u bit could be controlled by udit bit as follows; when udit bit is ?0?, u bit is always ?0?. when udit bit is ?1?, the recovered u bits are used for dit (dir/dit loop mode of u bit). this mode is only available when pll is locked and the master mode. ops02 ops01 ops00 output data 0 0 0 rx0 default 0 0 1 rx1 0 1 0 rx2 0 1 1 rx3 1 0 0 rx4 1 0 1 rx5 1 1 0 rx6 1 1 1 rx7 table 26. output data select for tx0 dit ops12 ops11 ops10 output data 0 0 0 0 rx0 0 0 0 1 rx1 0 0 1 0 rx2 0 0 1 1 rx3 0 1 0 0 rx4 0 1 0 1 rx5 0 1 1 0 rx6 0 1 1 1 rx7 1 x x x daux2 default table 27. output data select for tx1 lrck ( i 2 s ) vin l0 r0 l1 daux l0 r0 l1 r191 r1 (mono mode) (normal mode) lrck (except i 2 s) l0 r0 l1 l0/r0 l1/r1 l191/r191 r1 figure 22. daux2 and vin input timings
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 50 - biphase signal input/output circuit rx AK4588 0.1uf 75 ? coax 75 ? figure 23. consumer input circuit (coaxial input) note: in case of coaxial input, if a coupling level to this input from the next rx input line pattern exceeds 50mv, there is a possibility to occur an incorrect operation. in this case, it is possible to lower the coupling level by adding this decoupling capacitor. rx AK4588 470 o/e optical receiver optical fiber figure 24. consumer input circuit (optical input) in case of coaxial input, as the input level of rx line is small, in serial mode, be careful not to crosstalk among rx input lines. for example, by inserting the shield pattern among them. in parallel mode, only one channel input (rx1) is available and rx2-4 change to other pins for audio format control. those pins must be fixed to ?h? or ?l?. the AK4588 includes the tx output buffer. the output level meets combination 0.5v+/-20% using the external resistor network. the t1 in figure 25 is a transformer of 1:1. tx dvss 100 t1 75 ? cable 330 figure 25. tx external resistor network
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 51 - q-subcode buffers the AK4588 has q-subcode buffer for cd application. the AK4588 takes q-subcode into registers by following conditions. 1. the sync word (s0,s1) is constructed at least 16 ?0?s. 2. the start bit is ?1?. 3. those 7bits q-w follows to the start bit. 4. the distance between two start bits are 8-16 bits. the qint bit in the control register goes ?1? when the new q-subcode differs from old one, and goes ?0? when qint bit is read. 1 2 3 4 5 6 7 8 * s0 0 0 0 0 0 0 0 0 0? s1 0 0 0 0 0 0 0 0 0? s2 1 q2 r2 s2 t2 u2 v2 w2 0? s3 1 q3 r3 s3 t3 u3 v3 w3 0? : : : : : : : : : : s97 1 q97 r97 s97 t97 u97 v97 w97 0? s0 0 0 0 0 0 0 0 0 0? s1 0 0 0 0 0 0 0 0 0? s2 1 q2 r2 s2 t2 u2 v2 w2 0? s3 1 q3 r3 s3 t3 u3 v3 w3 0? : : : : : : : : : : (*) number of "0" : min=0; max=8. figure 26. configuration of u-bit(cd) q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 q16 q17 q18 q19 q20 q21 q22 q23 q24 q25 ctrl adrs track number index q26 q27 q28 q29 q30 q31 q32 q33 q34 q35 q36 q37 q38 q39 q40 q41 q42 q43 q44 q45 q46 q47 q48 q49 minute second frame q50 q51 q52 q53 q54 q55 q56 q57 q58 q59 q60 q61 q62 q63 q64 q65 q66 q67 q68 q69 q70 q71 q72 q73 zero absolute minute absolute second q74 q75 q76 q77 q78 q79 q80 q81 q82 q83 q84 q85 q86 q87 q88 q89 q90 q91 q92 q93 q94 q95 q96 q97 absolute frame crc g(x)=x^16+x^12+x^5+1 figure 27. q-subcode addr register name d7 d6 d5 d4 d3 d2 d1 d0 16h q-subcode address / control q9 q8 q3 q2 17h q-subcode track q17 q16 q11 q10 18h q-subcode index 19h q-subcode minute 1ah q-subcode second 1bh q-subcode frame 1ch q-subcode zero 1dh q-subcode abs minute 1eh q-subcode abs second 1fh q-subcode abs frame q81 q80 q75 q74 figure 28. q-subcode register q
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 52 - error handling there are the following eight events that make int0/1 pins ?h?. int0/1 pins show the status of following conditions. 1. unlock: ?1? when the pll loses lock. AK4588 loses lock when the distance between two preambles is not correct or when those preambles are not correct. 2. par: ?1? when parity error or biphase coding error is detected, and keeps ?1? until this register is read. updated every sub-frame cycle. reading this register resets itself. 3. auto: ?1? when non-pcm bitstream is detected. updated every 4096 frames cycle. 4. dtscd: ?1? when dts-cd bitstream is detected. updated every dts-cd sync cycle. 5. audion: ?1? when the ?audio? bit in recovered channel status indicates ?1?. updated every block cycle. 6. pem: ?1? when ?pem? in recovered channel status indicates ?1?. updated every block cycle. 7. qint: ?1? when q-subcode differ from old one, and keeps ?1? until this register is read. updated every sync code cycle for q-subcode. reading this register resets itself. 8. cint: ?1? when received c bits differ from old one, and keeps ?1? until this register is read. updated every block cycle. reading this register resets itself. both int0/1 are fixed to ?l? when the pll is off (cm1,0= ?01?). once the int0 pin goes to ?h?, this pin holds ?h? for 1024/fs cycles (this value can be changed by efh0/1 bits) after those events are removed. int1 pin goes to ?l? at the same time when those events are removed. each int0/1 pins can mask those eight events individually. once par, qint and cint bit goes to ?1?, those registers are held to ?1? until those registers are read. while the AK4588 loses lock, registers regarding c-bit or u-bits are not initialized and keep previous value. int0/1 pin output the ored signal among those eight events. however, each events can be masked by each mask bits. when each bit masks those events, the event does not affect int0/1 pins operation (those mask do not affect those registers (unlock, par, etc.) themselves. once int0 pin goes ?h?, it maintains ?h? for 1024/fs cycles (this value can be changed by efh0-1 bits) after the all events are removed. once those par, qint or cint bit goes ?1?, it holds ?1? until reading those registers. while the AK4588 loses lock, the channel status an q-subcode bits are not updated and holds the previous data. at initial state, int0 outputs the ored signal between unlock and par, int1 outputs the ored signal among auto, dtscd and audion. register pin unlock par auto dtscd audion pem qint cint sdto2 v tx 1 x x x x x x x ?l? ?l? output 0 1 x x x x x x previous data output output 0 0 1 x x x x x output output output 0 0 x 1 x x x x output output output 0 0 x x 1 x x x output output output 0 0 x x x 1 x x output output output 0 0 x x x x 1 x output output output 0 0 x x x x x 1 output output output table 28. error handling
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 53 - error (unlock, par,..) int1 pin sdto2 (unlock) mcko,bick2,lrck2 (unlock) previous data register (par,cint,qint) hold ?1? command read 06h mcko,bick2,lrck2 (except unlock) (fs: around 20khz) sdto2 (par error) hold time = 0 reset (error) sdto2 (others) normal operation int0 pin hold time (max: 4096/fs) register (others) free run vpin (unlock) vpin (except unlock) figure 29. int0/1 pin timing
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 54 - int0/1 pin ="h" no ye s ye s initialize pd pin ="l" to "h" read 06h mute dac output read 06h no (each error handling) read 06h (resets registers) int0/1 pin ="h" release muting figure 30. error handling sequence example 1
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 55 - int1 pin ="h" no ye s initialize pd pin ="l" to "h" read 06h read 06h and detect qsub= ?1? no (read q-buffer) new data is valid int1 pin ="l" qcrc = ?0? ye s ye s new data is invalid no figure 31. error handling sequence example 2 (for q/cint)
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 56 - audio serial interface format the dif0, dif1 and dif2 pins can select eight serial data formats as shown in table 29. in all formats the serial data is msb-first, 2's compliment format. the sdto2 is clocked out on the falling edge of bick2 and the daux2 is latched on the rising edge of bick2. bick2 outputs 64fs clock in mode 0-5. mode 6-7 are slave modes, and bick2 is available up to 128fs at fs=48khz. in the format equal or less than 20bit (mode0-2), lsbs in sub-frame are truncated. in mode 3-7, the last 4lsbs are auxiliary data (see figure 32). when using master mode, bick2 and krck2 output pins become hi-z in pdn pin = ?l? and from pdn pin = ?h? till master mode. when the parity error, biphase error or frame length error occurs in a sub-frame, AK4588 continues to output the last normal sub-frame data from sdto2 repeatedly until the error is removed. when the unlock error occurs, AK4588 output ?0? from sdto2. in case of using daux2 pin, the data is transformed and output from sdto2. daux2 pin is used in clock operation mode 1, 3 and unlock state of mode 2. the input data format to daux2 should be left justified except in mode5 and 7(table 29). in mode5 or 7, both the input data format of daux2 and output data format of sdto2 are i 2 s. mode6 and 7 are slave mode that is corresponding to the master mode of mode4 and 5. in salve mode, lrck2 and bick2 should be fed with synchronizing to mcko1/2. 0 3 4 7 8 11 12 27 28 29 30 31 preamble aux. lsb msb vuc p sub-frame of iec60958 0 23 AK4588 audio data (msb first) lsb msb figure 32. bit configuration lrck2 bick2 mode dif2 dif1 dif0 daux2 sdto2 i/ o i/ o 0 0 0 0 24bit, left justified 16bit, right justified h/l o 64fs o 1 0 0 1 24bit, left justified 18bit, right justified h/l o 64fs o 2 0 1 0 24bit, left justified 20bit, right justified h/l o 64fs o 3 0 1 1 24bit, left justified 24bit, right justified h/l o 64fs o 4 1 0 0 24bit, left justified 24bit, left justified h/l o 64fs o 5 1 0 1 24bit, i 2 s 24bit, i 2 s l/h o 64fs o 6 1 1 0 24bit, left justified 24bit, left justified h/l i 64-128fs i default 7 1 1 1 24bit, i 2 s 24bit, i 2 s l/h i 64-128fs i table 29. audio data format
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 57 - lrck2 bick2 ( 0:64fs ) sdto2 0 1 2 31 0 1 15:msb, 0:lsb lch data rch data 15 17 16 15 31 0 1 2 17 16 01 0 1 15 14 14 15 figure 33. mode 0 timing lrck2 bick2 ( 0:64fs ) sdto2 0 1 2 31 0 1 23:msb, 0:lsb lch data rch data 9 11 10 9 31 0 1 2 11 10 01 0 1 12 21 20 20 21 12 22 23 22 23 figure 34. mode 3 timing lrck2 bick2 ( 64fs ) sdto2 0 1 2 31 0 1 23:msb, 0:lsb lch data rch data 21 23 22 21 31 0 1 2 23 22 23 22 2 24 1 0 0 1 24 21 22 23 32 23 22 figure 35. mode 4, 6 timing mode4 : lrck2, bick2 : output mode6 : lrck2, bick2 : input lrck2 bick2 ( 64fs ) sdto2 0 1 2 31 0 1 23:msb, 0:lsb lch data rch data 23 22 21 31 0 1 2 23 22 23 22 24 1 0 24 32 23 25 2 0 1 21 22 23 25 figure 36. mode 5, 7 timing mode5 : lrck2, bick2 : output mode7 : lrck2, bick2 : input
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 58 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h clk & power down control cs12 bcu cm1 cm0 ocks1 ocks0 pwn rstn 01h format & de-em control mono dif2 dif1 dif0 deau dem1 dem0 dfs 02h input/ output control 0 tx1e ops12 ops11 ops10 tx0e ops02 ops01 ops00 03h input/ output control 1 efh1 efh0 udit tlr dit ips2 ips1 ips0 04h int0 mask mqit0 maut0 mcit0 mulk0 mdts0 mpe0 maud0 mpar0 05h int1 mask mqit1 maut1 mcit1 mulk1 mdts1 mpe1 maud1 mpar1 06h receiver status 0 qint auto cint unlck dtscd pem audion par 07h receiver status 1 fs3 fs2 fs1 fs0 0 v qcrc ccrc 08h rx channel status byte 0 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 09h rx channel status byte 1 cr15 cr14 cr13 cr12 cr11 cr10 cr9 cr8 0ah rx channel status byte 2 cr23 cr22 cr21 cr20 cr19 cr18 cr17 cr16 0bh rx channel status byte 3 cr31 cr30 cr29 cr28 cr27 cr26 cr25 cr24 0ch rx channel status byte 4 cr39 cr38 cr37 cr36 cr35 cr34 cr33 cr32 0dh tx channel status byte 0 ct7 ct6 ct5 ct4 ct3 ct2 ct1 ct0 0eh tx channel status byte 1 ct15 ct14 ct13 ct12 ct11 ct10 ct9 ct8 0fh tx channel status byte 2 ct23 ct22 ct21 ct20 ct19 ct18 ct17 ct16 10h tx channel status byte 3 ct31 ct30 ct29 ct28 ct27 ct26 ct25 ct24 11h tx channel status byte 4 ct39 ct39 ct39 ct39 ct39 ct39 ct39 ct32 12h burst preamble pc byte 0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 13h burst preamble pc byte 1 pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 14h burst preamble pd byte 0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 15h burst preamble pd byte 1 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 16h q-subcode address / control q9 q8 q7 q6 q5 q4 q3 q2 17h q-subcode track q17 q16 q15 q14 q13 q12 q11 q10 18h q-subcode index q25 q24 q23 q22 q21 q20 q19 q18 19h q-subcode minute q33 q32 q31 q30 q29 q28 q27 q26 1ah q-subcode second q41 q40 q39 q38 q37 q36 q35 q34 1bh q-subcode frame q49 q48 q47 q46 q45 q44 q43 q42 1ch q-subcode zero q57 q56 q55 q54 q53 q52 q51 q50 1dh q-subcode abs minute q65 q64 q63 q62 q61 q60 q59 q58 1eh q-subcode abs second q73 q72 q71 q70 q69 q68 q67 q66 1fh q-subcode abs frame q81 q80 q79 q78 q77 q76 q75 q74 when pdn pin goes ?l?, the registers are initialized to their default values. when rstn bit goes ?0?, the internal timing is reset and the registers are initialized to their default values. all data can be written to the register even if pwn bit is ?0?.
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 59 - register definitions reset & initialize addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h clk & power down control cs12 bcu cm1 cm0 ocks1 ocks0 pwn rstn r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 1 0 0 0 0 1 1 rstn: timing reset & register initialize 0: reset & initialize 1: normal operation pwn: power down 0: power down 1: normal operation ocks1-0: master clock frequency select cm1-0: master clock operation mode select bcu: block start & c/u output mode when bcu=1, the three output pins(bout, cout, uout) become to be enabled. the block signal goes high at the start of frame 0 and remains high until the end of frame 31. cs12: channel status select 0: channel 1 1: channel 2 selects which channel status is used to derive c-bit buffers, audion, pem, fs3, fs2, fs1, fs0, pc and pd. the de-emphasis filter is controlled by channel 1 in the parallel mode. format & de-emphasis control addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h format & de-em control mono dif2 dif1 dif0 deau dem1 dem0 dfs r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 1 1 0 1 0 1 0 dfs: 96khz de-emphasis control dem1-0: 32, 44.1, 48khz de-emphasis control (see table 24.) deau: de-emphasis auto detect enable 0: disable 1: enable dif2-0: audio data format control (see table 29.) mono: double sampling frequency mode enable 0: stereo mode 1: mono mode
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 60 - input/output control addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h input/ output control 0 tx1e ops12 ops11 ops10 tx0e ops02 ops01 ops00 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 0 0 0 1 0 0 0 ops02-00: output through data select for tx0 pin ops12-10: output through data select for tx1 pin tx0e: tx0 output enable 0: disable. tx0 pin outputs ?l?. 1: enable tx1e: tx1 output enable 0: disable. tx1 pin outputs ?l?. 1: enable addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h input/ output control 1 efh1 efh0 udit tlr dit ips2 ips1 ips0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 1 0 0 1 0 0 0 ips2-0: input recovery data select dit: through data/transmit data select for tx1 pin 0: through data (rx data). 1: transmit data (daux2 data). tlr: double sampling frequency mode channel select for dit(stereo) 0: l channel 1: r channel udit: u bit control for dit 0: u bit is fixed to ?0? 1: recovered u bit is used for dit (loop mode for u bit) efh1-0: interrupt 0 pin hold count select 00: 512 lrck2 01: 1024 lrck2 10: 2048 lrck2 11: 4096 lrck2
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 61 - mask control for int0 addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h int0 mask mqi0 mat0 mci0 mul0 mdts0 mpe0 man0 mpr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 0 1 1 1 0 mpr0: mask enable for par bit man0: mask enable for audn bit mpe0: mask enable for pem bit mdts0: mask enable for dtscd bit mul0: mask enable for unlock bit mci0: mask enable for cint bit mat0: mask enable for auto bit mqi0: mask enable for qint bit 0: mask disable 1: mask enable mask control for int1 addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h int1 mask mqi1 mat1 mci1 mul1 mdts1 mpe1 man1 mpr1 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 0 1 1 0 1 0 1 mpr1: mask enable for par bit man1: mask enable for audn bit mpe1: mask enable for pem bit mdts1: mask enable for dtscd bit mul1: mask enable for unlock0 bit mci1: mask enable for cint bit mat1: mask enable for auto bit mqi1: mask enable for qint bit 0: mask disable 1: mask enable
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 62 - receiver status 0 addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h receiver status 0 qint auto cint unlck dtscd pem audion par r/w rd rd rd rd rd rd rd rd default 0 0 0 0 0 0 0 0 par: parity error or biphase error status 0:no error 1:error it is ?1? if parity error or biphase error is detected in the sub-frame. audion: audio bit output 0: audio 1: non audio this bit is made by encoding channel status bits. pem: pre-emphasis detect. 0: off 1: on this bit is made by encoding channel status bits. dtscd: dts-cd auto detect 0: no detect 1: detect unlck: pll lock status 0: locked 1: out of lock cint: channel status buffer interrupt 0: no change 1: changed auto: non-pcm auto detect 0: no detect 1: detect qint: q-subcode buffer interrupt 0: no change 1: changed qint, cint and par bits are initialized when 06h is read. receiver status 1 addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h receiver status 1 fs3 fs2 fs1 fs0 0 v qcrc ccrc r/w rd rd rd rd rd rd rd rd default 0 0 0 1 0 0 0 0 ccrc: cyclic redundancy check for channel status 0:no error 1:error qcrc: cyclic redundancy check for q-subcode 0:no error 1:error v: validity of channel status 0:valid 1:invalid fs3-0: sampling frequency detection (see table 20.)
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 63 - receiver channel status addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h rx channel status byte 0 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 09h rx channel status byte 1 cr15 cr14 cr13 cr12 cr11 cr10 cr9 cr8 0ah rx channel status byte 2 cr23 cr22 cr21 cr20 cr19 cr18 cr17 cr16 0bh rx channel status byte 3 cr31 cr30 cr29 cr28 cr27 cr26 cr25 cr24 0ch rx channel status byte 4 cr39 cr38 cr37 cr36 cr35 cr34 cr33 cr32 r/w rd default not initialized cr39-0: receiver channel status byte 4-0 transmitter channel status addr register name d7 d6 d5 d4 d3 d2 d1 d0 0dh tx channel status byte 0 ct7 ct6 ct5 ct4 ct3 ct2 ct1 ct0 0eh tx channel status byte 1 ct15 ct14 ct13 ct12 ct11 ct10 ct9 ct8 0fh tx channel status byte 2 ct23 ct22 ct21 ct20 ct19 ct18 ct17 ct16 10h tx channel status byte 3 ct31 ct30 ct29 ct28 ct27 ct26 ct25 ct24 11h tx channel status byte 3 ct39 ct38 ct37 ct36 ct35 ct34 ct335 ct32 r/w r/w default 0 ct39-0: transmitter channel status byte 4-0 burst preamble pc/pd in non-pcm encoded audio bitstreams addr register name d7 d6 d5 d4 d3 d2 d1 d0 12h burst preamble pc byte 0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 13h burst preamble pc byte 1 pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 14h burst preamble pd byte 0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 15h burst preamble pd byte 1 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 r/w rd default not initialized pc15-0: burst preamble pc byte 0 and 1 pd15-0: burst preamble pd byte 0 and 1
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 64 - q-subcode buffer addr register name d7 d6 d5 d4 d3 d2 d1 d0 16h q-subcode address / control q9 q8 q7 q6 q5 q4 q3 q2 17h q-subcode track q17 q16 q15 q14 q13 q12 q11 q10 18h q-subcode index q25 q24 q23 q22 q21 q20 q19 q18 19h q-subcode minute q33 q32 q31 q30 q29 q28 q27 q26 1ah q-subcode second q41 q40 q39 q38 q37 q36 q35 q34 1bh q-subcode frame q49 q48 q47 q46 q45 q44 q43 q42 1ch q-subcode zero q57 q56 q55 q54 q53 q52 q51 q50 1dh q-subcode abs minute q65 q64 q63 q62 q61 q60 q59 q58 1eh q-subcode abs second q73 q72 q71 q70 q69 q68 q67 q66 1fh q-subcode abs frame q81 q80 q79 q78 q77 q76 q75 q74 r/w rd default not initialized
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 65 - burst preambles in non-pcm bitstreams 0 16 bits of bitstream 34 7 811 12 27 28 29 30 31 preamble aux. lsb msb v u c p sub-frame of iec958 015 pa pb pc pd burst_payload stuffing repetition time of the burst figure 37. data structure in iec60958 preamble word length of field contents value pa 16 bits sync word 1 0xf872 pb 16 bits sync word 2 0x4e1f pc 16 bits burst info see table 31 pd 16 bits length code numbers of bits table 30. burst preamble words
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 66 - bits of pc value contents repetition time of burst in iec60958 frames 0-4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16-31 data type null data dolby ac-3 data reserved pause mpeg-1 layer1 data mpeg-1 layer2 or 3 data or mpeg-2 without extension mpeg-2 data with extension mpeg-2 aac adts mpeg-2, layer1 low sample rate mpeg-2, layer2 or 3 low sample rate reserved dts type i dts type ii dts type iii atrac atrac2/3 reserved 4096 1536 384 1152 1152 1024 384 1152 512 1024 2048 512 1024 5, 6 0 reserved, shall be set to ?0? 7 0 1 error-flag indicating a valid burst_payload error-flag indicating that the burst_payload may contain errors 8-12 data type dependent info 13-15 0 bit stream number, shall be set to ?0? table 31. fields of burst info pc
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 67 - non-pcm bitstream timing 1) when non-pcm preamble is not coming within 4096 frames, pa pc 1 pd 1 pb pa pc 2 pd 2 pb pa pc 3 pd 3 pb ?0? pc 1 pc 2 ?0? pd 1 pd 2 pd 3 pc 3 pdn pin bit stream auto bit pc register pd register re p etition time >4096 frames figure 38. timing example 1 2) when non-pcm bitstream stops (when mulk0=0), pa pc 1 pd 1 pb stop pa pc n pd n pb pc 0 pc 1 pd 0 pd 1 pd n pc n int0 pin bit stream auto bit pc register pd re g iste r int0 hold time 2~3 syncs (b,m or w) <20ms (lock time) asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 68 - operation overview (adc/dac part, dir/dit part) serial control interface AK4588 has two registers, which are adc/dac part (ak4628 compatible) and dir/dit part (ak4114 compatible). each register is set by chip address pin. (1). 4-wire serial control mode (i2c= ?l?) the internal registers may be either written or read by the 4-wire p interface pins: csn, cclk, cdti & cdto. the data on this interface consists of chip address (2bits, adc/dac part register is set by cad1/0 pins. dir/dit part c1-0 bits are fixed to ?00?), read/write (1bit), register address (msb first, 5bits) and control data (msb first, 8bits). address and data is clocked in on the rising edge of cclk and data is clocked out on the falling edge. for write operations, data is latched after the 16th rising edge of cclk, after a high-to-low transition of csn. for read operations, the cdto output goes high impedance after a low-to-high transition of csn. the maximum speed of cclk is 5mhz. pdn pin = ?l? resets the registers to their default values. when the state of p/s pin is changed, the AK4588 should be reset by pdn pin = ?l?. register of adc/dac part can not read. cdti cclk csn c1 0 1234567 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a 1 a 2 a3 a 4 r/w c0 a 0d0 d1 d2 d3 cdto hi-z write cdti c1 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3 cdto hi-z read d4 d5 d6 d7 d0 d1 d2 d3 hi-z c1-c0: chip address: (regarding adc/dac part, register is set by cad1/0 pins. this chip address must be set except ?00?.) (fixed to ?00? for dir/dit part) r/w: read/write (0:read, 1:write) a4-a0: register address d7-d0: control data figure 40. 4-wire serial control i/f timing
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 69 - (2). i 2 c bus control mode (i2c= ?h?) AK4588 supports the standard-mode i 2 c-bus (max : 100khz). then AK4588 does not support a fast-mode i 2 c-bus system (max: 400khz). (2)-1. data transfer all commands are preceded by a start condition. after the start condition, a slave address is sent. after the AK4588 recognizes the start condition, the device interfaced to the bus waits for the slave address to be transmitted over the sda line. if the transmitted slave address matches an address for one of the devices, the designated slave device pulls the sda line to low (acknowledge). the data transfer is always terminated by a stop condition generated by the master device. (2)-1-1. data validity the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low except for the start and the stop condition. scl sda data line stable : data valid change of data allowed figure 41. data transfer (2)-1-2. start and stop condition a high to low transition on the sda line while scl is high indicates a start condition. all sequences start from the start condition. a low to high transition on the sda line while scl is high defines a stop condition. all sequences end by the stop condition. scl sda stop condition start condition figure 42. start and stop conditions
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 70 - (2)-1-3. acknowledge acknowledge is a software convention used to indicate successful data transfers. the transmitting device w ill release the sda line (high) after transmitting eight bits. the receiver must pull down the sda line during the acknowledge clock pulse so that that it remains stable ?l? during ?h? period of this clock pulse. the AK4588 will generates an acknowledge after each byte has been received. in the read mode, the slave, the AK4588 will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition. scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition clock pulse for acknowledge not acknowledge figure 43. acknowledge on the i 2 c-bus (2)-1-4. first byte the first byte, which includes seven bits of slave address and one bit of r/w bit, is sent after the start condition. if the transmitted slave address matches an address for one of the device, the receiver who has been addressed pulls down the sda line. the most significant five bits of the slave address are fixed as ?00100?. the next two bits are cad1 and cad0 (device address bits). these two bits identify the specific device on the bus. the hard-wired input pins (cad1 pin and cad0 pin) set them. the eighth bit (lsb) of the first byte (r/w bit) defines whether a write or read condition is requested by the master. a ?1? indicates that the read operation is to be executed. a ?0? indicates that the write operation is to be executed. 0 0 1 0 0 cad1 cad0 r/w (regarding adc/dac part, register is set by cad1/0 pins. this chip address must be set except ?00?.) (fixed to ?00? for dir/dit part) figure 44. the first byte
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 71 - (2)-2. write operations set r/w bit = ?0? for the write operation of the AK4588. after receipt the start condition and the first byte, the AK4588 generates an acknowledge, and awaits the second byte (register address). the second byte consists of the address for control registers of AK4588. the format is msb first, and those most significant 3-bits are ?don?t care?. * * * a4 a3 a2 a1 a0 (*: don?t care) figure 45. the second byte after receipt the second byte, the AK4588 generates an acknowledge, and awaits the third byte. those data after the second byte contain control data. the format is msb first, 8bits. d7 d6 d5 d4 d3 d2 d1 d0 figure 46. byte structure after the second byte the AK4588 is capable of more than one byte write operation by one sequence. after receipt of the third byte, the AK4588 generates an acknowledge, and awaits the next data again. the master can transmit more than one words instead of terminating the write cycle after the first data word is transferred. after the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically. if the address exceed 1fh prior to generating the stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. sda s t a r t a c k a c k s slave address a c k register address(n) data(n) p s t o p data(n+x) a c k data(n+1) figure 47. write operation
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 72 - (2)-3. read operations set r/w bit = ?1? for the read operation of the AK4588. after transmission of a data, the master can read next address?s data by generating the acknowledge instead of terminating the write cycle after the receipt the first data word. after the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically. if the address exceed 1fh prior to generating the stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the AK4588 supports two basic read operations: current address read and random read. adc/dac part register can not read. (2)-3-1. current address read the AK4588 contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next current read operation would access data from the address n+1. after receipt of the slave address with r/w bit set to ?1?, the ak 4588 generates an acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address counter by 1. if the master does not generate an acknowledge to the data but generate the stop condition, the AK4588 discontinues transmission sda s t a r t a c k a c k s slave address a c k data(n) data(n+1) p s t o p data(n+x) a c k data(n+2) figure 48. current address read (2)-3-2. random read random read operation allows the master to access any memory location at random. prior to issuing the slave address with the r/w bit set to ?1?, the master must first perform a ?dummy? write operation. the master issues the start condition, slave address(r/w=?0?) and then the register address to read. after the register address?s acknowledge, the master immediately reissues the start condition and the slave address with the r/w bit set to ?1?. then the AK4588 generates an acknowledge, 1byte data and increments the internal address counter by 1. if the master does not generate an acknowledge to the data but generate the stop condition, the AK4588 discontinues transmission. sda s t a r t a c k a c k ss s t a r t slave address word address(n) slave address a c k data(n) a c k p s t o p data(n+x) a c k data(n+1) figure 49. random read
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 73 - system design figure 50 shows the system connection diagram. an evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. condition: i 2 c serial control mode tx1 int1 1 a k4588 + 10u a udio dsp 2 3 4 5 6 7 8 9 10 11 60 59 58 57 56 55 54 53 52 51 50 bout tvdd dvdd dvss test3 mcko1 vout bick2 l rck2 test1 n c a vs s av dd vref h vco m rin li n lout1 rout2 n c 80 79 78 77 76 75 74 73 72 71 70 tx 0 mcl k vi n daux2 i2 c rx 7 cad1 rx 4 pvd d r 21 22 23 24 25 26 27 28 29 30 31 sd a daux1 sdti3 sdti2 sdti1 xtl1 xtl0 pdn dzf2 dzf1 lout4 0 . 1 u s/pdif sources s/pdif out (mpeg/ac3 ) a nalo g 5v a nalog ground digital ground digital 5v micro controller 5 (shield) + 2 . 2 u 0 . 1 u 12k + 0.1u 10u + x?tal 0.1u 10u c c 1 2 13 14 15 16 69 68 67 66 65 32 33 34 35 36 49 48 47 46 45 sdto2 uout mcko2 cout xto xt i scl csn sdti4 mast er nc nc n c rout1 rx 0 rx1 test 2 cad 0 rx5 rx 6 int 0 mute (shi e ld) sdto1 l rck1 cdto 17 18 19 20 bick1 nc lout3 nc 37 38 39 40 rout4 lout2 rout3 nc 44 43 42 41 n c rx3 n c rx 2 64 63 62 61 pvs s + 3.3v to 5v di g ital a udio dsp (mpeg/ac3) (micro controller) a udio dsp (mpeg/ac3) micro controlle r mute mute mute (shield) (shield) (shield) mute mute mute mute (shi e ld) (shi e ld) (shi e ld) (shi e ld) (shi e ld) (s/pdif source) (s/pdif sources) micro cont roller figure 50. typical connection diagram notes: - ?c? depends on the crystal. - avss, dvss and pvss must be connected the same analog ground plane. - digital signals, especially clocks, should be kept away from the r pin in order to avoid an effect to the clock jitter performance. - in case of coaxial input, ground of rca connector and terminator should be connected to pvss of the AK4588
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 74 - with low impedance on pc board.
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 75 - 1. grounding and power supply decoupling the AK4588 requires careful attention to power supply and grounding arrangements. avdd, dvdd and pvdd are usually supplied from analog supply in system. alternatively if avdd, dvdd and pvdd are supplied separately, the power up sequence is not critical. avss, dvss and pvss of the AK4588 must be connected to analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the AK4588 as possible, with the small value ceramic capacitor being the nearest. 2. voltage reference inputs the voltage of vrefh sets the analog input/output range. vrefh pin is normally connected to avdd with a 0.1f ceramic capacitor. vcom is a signal ground of this chip. an electrolytic capacitor 2.2f parallel with a 0.1f ceramic capacitor attached to vcom pin eliminates the effects of high frequency noise. no load current may be drawn from vcom pin. all signals, especially clocks, should be kept away from the vrefh and vcom pins in order to avoid unwanted coupling into the AK4588. 3. analog inputs adc inputs are single-ended and internally biased to vcom. the input signal range scales with the supply voltage and nominally 0.6 x vrefh vpp (typ). the adc output data format is 2?s compliment. the dc offset is removed by the internal hpf. the AK4588 samples the analog inputs at 64fs. the digital filter rejects noise above the stop band except for multiples of 64fs. the AK4588 includes an anti-aliasing filter (rc filter) to attenuate a noise around 64fs. 4. analog outputs the analog outputs are also single-ended and centered around the vcom voltage. the input signal range scales with the supply voltage and nominally 0.6 x vrefh vpp. the dac input data format is 2?s complement. the output voltage is a positive full scale for 7fffffh(@24bit) and a negative full scale for 800000h(@24bit). the ideal output is vcom voltage for 000000h(@24bit). the internal analog filters remove most of the noise generated by the delta-sigma modulator of dac beyond the audio passband. dc offsets on analog outputs are eliminated by ac coupling since dac outputs have dc offsets of a few mv.
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 76 - package 80-pin lqfp ( unit : mm ) 14.00.2 12.00.2 0.50 1 20 21 40 41 60 61 80 12.00.2 14.00.2 1.25typ 0.08 m 0.125 +0.10 -0.05 0.500.1 1.85max 0.10 +0.15 -0.10 1.400.2 0.10 0.200.1 0 ~ 10 material & lead finish package: epoxy lead-frame: copper lead-finish soldering (pb free) plate
asahi kasei akm confidential [AK4588] rev0.9 2003/09 - 77 - marking AK4588vq xxxxxxx 1) pin #1 indication 2) date code: xxxxxxx(7 digits) 3) marking code: AK4588vq 4) asahi kasei logo important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized fo r use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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